techxclusives - digitally removing a dc offset (or dsp without math) - part 1.htm

Source codes for DSP Spartan 3

      <P><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DC3.gif"></P>
      <P>It may seem hard to believe that a subtractor can be an important DSP 
      function, but it clearly is! (It is also very well-supported by Virtex and 
      Spartan-II devices.) As with the basic adder function (see the previous 
      techXclusive "8×12 Does NOT Equal 12×8"), each "slice" of the device can 
      implement a 2-bit subtractor. Therefore, a simple 8-bit subtractor will 
      require 4 "slices". As this is such a basic function, it is supported well 
      in many design flows, including HDL and System Generator. </P>
      <P>
      <H4>Finding the DC Level</H4>
      <P>Although we have achieved our objective to remove the DC offset with 
      the subtractor, the process relied on me stating the DC value that was to 
      be removed. Clearly, we now need to find a way to derive that DC offset 
      value automatically. Although this will be a little more complicated, we 
      can again take an empirical approach to finding a solution with another 
      very common function, and avoid a lot of "DSP theory". </P>
      <P>In the analogue world, the simplest way to find the average DC level of 
      a signal is to smooth it with a capacitor. The larger the value of the 
      smoothing capacitor, the steadier the DC level (especially if there is a 
      load current). </P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DC4.gif"></P>
      <P>In theory, we need to look at a differential equation to solve this 
      simple circuit. However, if we take an instant in time, then simple linear 
      equations can be used:</P>
      <P>Voltage across the resister "R" is given by: v<FONT 
      size=1>i</FONT>-v<FONT size=1>o</FONT>.</P>
      <P>Therefore, the current flowing into the capacitor is given 
      by:<BR>i<FONT size=1>c</FONT> = (v<FONT size=1>i</FONT>-v<FONT 
      size=1>o</FONT>)/R.</P>
      <P>If the input voltage is higher than the average value "v<FONT 
      size=1>o</FONT>", the capacitor will charge. Likewise, if the input 
      voltage is lower than the average value, the current will be negative 
      (flowing out of the capacitor), and the capacitor will discharge.</P>
      <P>The linear equation for the charge on a capacitor is: Q = C.V = I.T 
</P>
      <P>So, for a constant current of "I" for a period of time "T", the voltage 
      on the capacitor will rise by the amount V = (I.T)/C </P>
      <P>Obviously, the larger value of C, then the smaller the change in 
      voltage for a given current and time. </P>
      <P>This means that we can derive a final formula that describes this 
      simple RC circuit: </P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DC5.gif"> 
      </P>
      <P>OK, I said I wasn't going to do mathematics, but this really is a 
      simple linear equation. During a period of time "<IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DCv.gif">T", 
      the voltage across the capacitor will change by an amount proportional to 
      the difference between the input voltage and the output voltage. This 
      equation is only valid if the duration of time "<IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DCv.gif">T" 
      is so small that the voltage change "<IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DCv.gif" 
      width=13>V<FONT size=1>o</FONT>" does not significantly change the value 
      of "(v<FONT size=1>i</FONT>-v<FONT size=1>o</FONT>)". </P>
      <P>The equation can be simplified to <IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DC6.gif"> 
      by using a constant value "k", which is set by the combination of "R", 
      "C", and the period of time over which each calculation is made "<IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DCv.gif">T". 
      At the end of each period, the output voltage becomes the previous value 
      of "V<FONT size=1>o</FONT>" plus the incremental value "<IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DCv.gif">V<FONT 
      size=1>o</FONT>".</P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DC7.gif"></P>
      <P>We can try a simple experiment to prove this formula. Setting values of 
      R=50<IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DCo.gif">, 
      C=100µF (a time constant of RC=5ms), and <BR><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DCv.gif">T=1ms, 
      then k=0.2. By applying a simple 10-volt step input, we can see that the 
      calculated output for each step of time generates the exponential charge 
      curve we would expect for such an RC circuit: </P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DC8.gif" 
      <p> 
      <H4></H4>
      <P>
      <P>The exciting thing is that we have calculated a set of values at 
      regular intervals using a simple linear equation to describe a complex 
      differential function. Since the points are calculated at regular 
      intervals, this means that we have just performed digital signal 
      processing to emulate an analogue function! </P>
      <P>With such a simple equation representing a smoothing capacitor RC 
      circuit, it becomes easy for this to be realised as a digital circuit. The 
      clock sets the sample rate to a register that holds the current "charge 
      voltage" value, with the clock frequency determining the period "<IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DCv.gif">T" 
      for each step. The rest of the equation is then formed by a subtractor, an 
      adder, and a multiplier: </P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DC9.gif"></P>
      <P>It is interesting to see that the major part of this circuit consists 
      of a multiplier feeding an accumulator. This forms the most common 
      building block seen in DSP, which is often called a "MAC" (multiply and 
      accumulate).</P>
      <P>The value of the coefficient value "k" will set the behavior of our 
      circuit. Given that k= [<IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DCv.gif">T 
      / (R.C)], and that we have now fixed <BR>"<IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DCv.gif">T" 
      by setting the clock rate, the value of "k" is inversely proportional to 
      the RC time constant being modeled.</P>
      <P>In the plots below, the circuit is connected to the original waveforms 
      that contain DC offsets. The sample rate is 8kHz (<IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DCv.gif">T 
      =125µs). We can see that using a smaller "k" value -- the equivalent of a 
      larger RC time constant -- results in a longer "charge up" period, but a 
      smoother resulting output. </P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DC10.gif"><BR><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DC11.gif"> 
      <BR></P>
      <P>As we would expect, there is a trade-off between the time taken to 
      reach the DC offset level and the smoothness of the final value 
      derived.</P>
      <P>
      <H4>Implementing the Fractional Coefficient Multiplier</H4>
      <P>Although the addition and subtraction blocks are simple, the multiplier 
      may be a cause for concern. Looking at the multiplier core in CORE 
      Generator™ (or constructing your own, possibly directly from a synthesis 
      tool), you will be faced with the fact that both inputs are defined as 
      integers. The requirement in this circuit is to take an integer value 
      (<I><FONT color=#0000ff><B><FONT 
      face="Times New Roman, Times, serif">v<FONT 
      size=1>i</FONT></FONT></B></FONT><FONT 
      face="Times New Roman, Times, serif"><B> - <FONT color=#ff3333>v<FONT 
      size=1>o</FONT></FONT></B></FONT></I> ); but then, as is common with many 
      DSP designs, you must multiply this by a value "k" that is less than one. 
      </P>
      <P>The solution to this is also very simple. It is called "fixed-point 
      arithmetic", but merely involves interpreting the bits of integer 
      arithmetic in a different way. Consider the effect of multiplying an 8-bit 
      integer by the binary pattern "0101":</P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DC12.gif"></P>
      <P>In this case, the "0101" pattern is the integer value +5<FONT 
      size=1>10</FONT>, and the multiplication is straightforward. The 
      multiplication of an 8-bit number and a 4-bit number forms a potential 
      12-bit product. </P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DC13.gif"> 
      </P>
      <P>Now the same binary pattern (0101) has been divided by 4; this happened 
      by inserting a binary point 2-bits from the right-hand side of the number, 
      and forming the value 1.25<FONT size=1>10</FONT>. However, the binary 
      pattern of the product is exactly the same as in the previous integer 
      case. </P>
      <P>Hence, the multiplier works exactly the same way with fractional 
      numbers as it does with integers. To interpret the product result 
      correctly, a binary point is inserted the same number of bits from the 
      right-hand side as in the input value. Notice how the bits to the left of 
      the point "1100000" represent the integer part of the result (96<FONT 
      size=1>10</FONT> ), and the bits to the right of the point represent the 
      fractional part of the result (0.25<FONT size=1>10</FONT>). </P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DC14.gif"> 
      </P>
      <P>In this last case, the binary point has been located 6 bits away from 
      the right-hand side of the original "0101" pattern. This divides the value 
      by <IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DCsuper.gif">= 
      64. It appears that the value must increase by 3 bits just to position the 
      binary point; again, however, the binary pattern of the product is exactly 
      the same as it was before and simply needs to be interpreted correctly. 
      The binary point is located 6 bits from the right side; hence, the integer 
      part to the left of the point is 6<FONT size=1>10</FONT>, and the 
      fractional part to the right of the point is 0.015625<FONT 
      size=1>10</FONT> (1/64).</P>
      <P>
      <H4></H4>
      <P>
      <P>Let's just take a moment to consider the options available to you for 
      implementing the multiplier in Virtex and Spartan-II devices:</P>
      <P>i) The latest Virtex-II devices have dedicated multipliers, and you 
      should use this feature unless you have more pressing uses for it in the 
      rest of your system design. Given the full variable nature of these 
      multipliers, we may even consider changing the value of "k" during the 
      acquisition process. By starting with a large value for "k", the circuit 
      will rapidly locate the approximate DC level. If you switch to smaller 
      values of "k", a very stable and smooth DC value will be achieved. This is 
      like having a variable resistor in the analogue RC circuit.</P>
      <P>ii) Simply allow a synthesis tool to create a multiplier for you. If 
      you do this, it is worth looking at what resources have been used, 
      particularly if your products are cost-sensitive.</P>
      <P>iii) Take a look at the CORE Generator "Multiplier" core. You can 
      generate efficient variable multipliers, but you can also specify a 
      constant coefficient multiplier that will be formed of fewer "slices". 
      Generally, the "k" value will be a constant. </P><B>The Digital "RC" 
      Circuit </B>
      <P></P>
      <P>This knowledge about fractional multiplier techniques can be used to 
      create a bit-accurate model of an "RC" circuit and, hence, digitally 
      detect the DC level of our input signal:</P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 1_files/DC15.gif"></P>
      <P>The input samples are 8 bits; therefore, we know that the DC content 
      must also lie within the same range (I hope you never have a DC offset 
      anywhere near the limits in your systems!). Since the DC detection circuit 
      will start at zero, and the DC offset is likely to be a very slow moving 
      level, we can use an 8-bit subtractor to form the difference signal 
      (<I><FONT color=#0000ff><B><FONT 
      face="Times New Roman, Times, serif">v<FONT 
      size=1>i</FONT></FONT></B></FONT><FONT 
      face="Times New Roman, Times, serif"><B> - <FONT color=#ff3333>v<FONT 
      size=1>o</FONT></FONT></B></FONT></I> ). </P>
      <P>Now comes the multiplication stage. I have selected an 8-bit × 8-bit 
      multiplier, which will produce a 16-bit product. The "k" value will be 
      less than unity because I have specified all bits to be to the right of 
      the binary point. It is worth noting that the difference signal is signed 
      (± values), but the coefficient "k" will always be positive. </P>
      <P>Hence, the range of available "k" values is from 0.0039 (1/256) to 
      0.9961 (255/256). Since values of more than 0.03 and higher would have a 
      large ripple (look back at the plots), it may be better to use fewer bits 
      for the value of "k", but retain the same binary bit position. However, 
      you may use the larger values of "k" to rapidly reach the DC level, and 
      then reduce them.</P>
      <P>The 16-bit product must be considered as consisting of an 8-bit integer 
      (left of the binary point) and an 8-bit fraction (right of the binary 
      point). Therefore, the accumulator must work with a full 16-bits. The 
      accumulation of the fractional values, as well as the integer parts of the 
      products, is required to ensure that the DC level is able to adjust even 
      when very small "k" values are used and very small products are being 
      generated.</P>
      <P>Finally, only the integer portion of the accumulated value represented 
      by the 8 most significant bits is used to identify the DC level that is to 
      be used by the signal-correcting subtractor we defined earlier. </P>
      <P>
      <H4>Part 1 Summary</H4>
      <P>
      <P>I hope that I have been able to show you that it is possible to 
      approach DSP in a very practical way. We have been able to take a simple 
      analogue circuit and represent it in the digital domain to create a very 
      efficient and practical function. If you also consider that the 
      accumulator, subtractors, and a multiplier are all able to operate in 
      excess of 100MHz in all devices, then we have also created a very high- 
      performance circuit that is able to take samples directly from the 
      majority of high performance A/D converters.</P>
      <P>In Part 2, I will look at how this circuit can be further 
optimised:</P>
      <P>First, I will reduce the size of the parallel circuit we have 
      constructed. Can you already see a way to remove the multiplier logic 
      altogether? Can you see anything else that can be removed? </P>
      <P>Then, I will look at how to use the SRL16E to efficiently create a 
      serial version of the circuit that is suitable for low sample rate 
      applications. The waveform we have considered here was at an audio 
      communications rate of 8KHz; it would be nice to trade some of the huge 
      performance that is possible in Spartan-II devices for a smaller and 
      lower-cost implementation.</P>
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