techxclusives - digitally removing a dc offset (or dsp without math) - part 2.htm

Source codes for DSP Spartan 3

      am going to adopt the second of these values as I consider that the low 
      ripple is much more desirable than the response time -- especially as even 
      100ms is relatively short. </P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 2_files/DC2-1.gif"></P>
      <P>Since the multiplication process only requires that the variable input 
      be multiplied by "1," the output product is the same as the input. 
      Clearly, there is no need for a real multiplier; the output product is the 
      same value, and the bit width is the same as the variable input. All that 
      is required is to apply the variable input value with the binary point 
      reassigned to the correct position. Our complete DC offset removal circuit 
      is then reduced to the following logic...</P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 2_files/DC2-2.gif"></P>
      <P>The circuit now consists only of an accumulator and two subtractors. 
      Care is required when connecting the variable difference signal (<I><FONT 
      color=#0000ff>v<FONT size=1>i</FONT></FONT> - <FONT color=#ff0033>v<FONT 
      size=1>o</FONT></FONT></I>) to the accumulator input. To represent that 
      the 8 bits are all fractional (to the right of the binary point), they are 
      applied to the least significant byte of the 16-bit input. However, the 
      upper byte must also be defined, and this must be achieved using sign 
      extension (replicate the MSB of the 8-bit value a further 8 times to form 
      either "00" or "FF" hexadecimal); this is so that the twos complement 
      logic of the accumulator will correctly add both positive and negative 
      values. </P>
      <P>With this very small "k" value, it is obvious why the accumulation of 
      the fractional parts (as well as the integer parts) must be performed. 
</P>
      <P>
      <H4>Removing a subtractor</H4>
      <P>
      <P>Having drawn out the DC level detector and the DC removing subtractor 
      on the same diagram for the first time, it may appear more obvious that 
      one of the subtractors is redundant. The corrected signal is the original 
      signal with the DC level subtracted from it. This means that the output is 
      the value <I><FONT color=#0000ff>v<FONT size=1>i</FONT></FONT> - <FONT 
      color=#ff0033>v<FONT size=1>o</FONT></FONT></I>, which is the same as the 
      difference signal being created by the subtractor within the DC detection 
      circuit. </P>
      <P>This means that the complete DC offset removal circuit can be reduced 
      to just one accumulator and one subtractor... </P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 2_files/DC2-3.gif"></P>
      <P>Using the simple but accurate rule that a 2-bit add or subtract 
      function fits into a "slice," then this circuit now only requires 12 
      "slices." For each additional bit of sample width, the subtractor and 
      accumulator will each increase by 1 bit and, accordingly, increase the 
      total size by 1 "slice." Therefore, with 16-bit input samples, the size 
      would increase to 20 "slices." As a parallel circuit, this can also 
      support a sample rate well in excess of 100MHz. </<P>
      <H4>Low Sample Rate Applications</H4>
      <P>
      <P>Although 12 and 20 "slices" may not sound like very much, it is still 
      6% to 10% of the smallest XC2S15 device, and this DC offset removal may 
      well be seen as just a pre-process to the main function. </P>
      <P>In a typical application, this DC offset removal may be required in a 
      telephone conferencing facility. Each of the input lines (represented by 
      digital samples) will ultimately be summed together within the system, and 
      the contribution of multiple small DC offsets may have an adverse effect 
      on the overall dynamics. The requirement for a DC offset removal circuit 
      on each line input would soon see all those 6-10% units of a device 
      mounting up to something significant. </P>
      <P>Also typical of audio telecommunications, data samples are transmitted 
      serially between units. These may be as packets within data frames, or 
      even directly from the A/D converter. The Texas Instruments TLC320AC01C 
      analogue Interface circuit (AIC) device uses a serial communications 
      protocol with 14-bit A/D samples being transmitted with the most 
      significant bit first as part of each 16-bit transfer... </P>
      <P align=center><IMG height=141 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 2_files/DC2-4.gif" 
      width=336></P>
      <P>To use the parallel implementation of the DC offset removal circuit, 
      such serial data samples would need to be applied to a 14-bit shift 
      register in order to read the sample in parallel. This requires an 
      additional 7 "slices." </P>
      <P>
      <H4>Staying Serial</H4>
      <P>Instead of converting to parallel, it is better to process the data 
      serially as well. Although this may take many clock cycles to achieve, 
      with sample rates as low as 8kHz, even a 10MHz clock provides 1250 clock 
      cycles in which to implement the task.</P>
      <P>In our circuit, we have to achieve the functionality of an accumulator 
      and a subtractor. In the serial processing form, these only have to 
      resolve 1 bit of the result each clock cycle and take on the form of a 
      1-bit full adder or 1-bit full subtractor. The functionality can be 
      derived from a truth table. The only special observation to be made is 
      that the process starts with the least significant bit first, and then 
      generates the result bit and a CARRY/BORROW flag for use in the 
      calculation of the next most significant bit of the process. During the 
      processing of the first bit (LSB), any previous carry/borrow status must 
      be ignored. This can be achieved by a "masking" signal. </P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 2_files/DC2-5.gif"></P>
      <P>The nice thing about these serial arithmetic functions is that however 
      complex the truth table, they fit perfectly into the 4-input look-up 
      tables of the Virtex and Spartan-II devices. Hence, an adder or subtractor 
      requires just one "slice" each.</P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 2_files/DC2-6.gif"><BR></P>
      <HR>

      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 2_files/DC2-7.gif"><BR></P>
      <P>To convert the adder into an accumulator, we need to add storage for 
      the accumulated value. In this case, the storage can be formed serially; 
      therefore, the SRL16E becomes the obvious selection. If a 16-bit 
      accumulator is not adequate, then using two SRL16E components forms a 
      complete 32-bit accumulator in just 2 "slices." The clock-enable can be 
      used to freeze the contents between bursts of sample processing 
      activity.</P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 2_files/DC2-8.gif"></P>
      <P>
      <H4>Back-to-Front Data</H4>
      <P>There is an issue concerning the order of the serial data. The serial 
      adder and subtractor functions work with least significant bit (LSB) 
      first; however, as shown by the communications with the TLC320AC01C, 
      serial samples may be derived with MSB first. The order of the data must 
      be changed, and this again is ideally suited to the SRL16E primitive….. 
      </P>
      <P><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 2_files/DC2-9.gif"></P>
      <P>The SRL16E also performs a conversion between clock rates. The serial 
      data clock can be applied to the SRL16E directly with no requirements for 
      a clock buffer, as all the flip-flops of the shift register are contained 
      in the same look-up table and share a common local clock with zero skew. 
      When the frame strobe is active (low), data is enabled to shift into the 
      SRL16E with MSB first. After the 16-bit transfer is completed, the data 
      remains static and can then be read via the embedded multiplexer, which is 
      a combinatorial process. A counter can select the required sample bits 
      and, of course, read them LSB first. </P><B>Some Careful Scheduling</B> 
      <P>The key to serial processing is to ensure that everything is using the 
      correct bits during each clock cycle. In this implementation, we have an 
      interesting case because the accumulator addition process starts with the 
      least significant bit of the "fraction" part of the DC offset, but the 
      subtraction must start with the least significant bit of the "integer" 
      part of the DC offset. This is easily solved by splitting the accumulator 
      storage into two shift register delays such that a tapping point is 
      achieved at the LSB of the integer storage point. </P>
      <P>In this implementation, I have considered that the input samples are 
      14-bits. This means that the serial subtraction process will take 14 clock 
      cycles. However, the accumulation process must be 22 bits, as it includes 
      the 8-bit fraction, and will therefore require 22 clock cycles. To apply 
      the 14-bit result of subtraction to the 22-bit accumulation process, we 
      must again sign extend. In the serial domain, the sign extension is nicely 
      achieved by holding the MSB bit generated by the subtractor static in a 
      flip-flop by de-asserting a clock enable at the end of the 14th clock 
      cycle. </P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 2_files/DC2-10.gif"></P>
      <P>
      <H4>State Machine Made Easy</H4>
      <P>The state machine to control each event is also simplified by the use 
      of SRL16E delays. This can be a form of "one-hot" state machine which is 
      allowed to become "cold" between bursts of activity required to process 
      each new data sample. The "hot" state is injected in the form of a single 
      clock cycle pulse that is applied co-incident with the LSB of the 
      serialised 14-bit data sample. </P>
      <P>Simple flip-flops delay this initial start pulse and ensure that the 
      serial subtractor and serial adder have the carry "mask" applied 
      co-incident with processing the LSB in each case. The SRL16 components are 
      used to delay the initial pulse for 14 and 22 clock cycles to control the 
      duration of the serial subtract and serial accumulation processes. In each 
      case, a flip-flop is set by the initial start pulse and enables the 
      process to begin. When the pulse emerges from the SRL16, it is used to 
      reset the flip-flop and, hence, stop the serial processing.</P>
      <P align=center><IMG 
      src="TechXclusives - Digitally Removing a DC Offset (or DSP Without Math) - Part 2_files/DC2-11.gif"></P><B>Summary</B> 

      <P>In this article, we have been able to see that by careful consideration 
      of coefficient values, real multiplier logic can be removed, significantly 
      reducing the size of a function. We then looked at serial processing and 
      how this is able to further reduce the size of an implementation for lower 
      sample rate applications. Indeed, we even saw that in this type of 
      application, the data samples are most likely provided in a serial format 
      anyway and prevent the requirement to convert to parallel for 
      processing.</P>
      <P>I am delighted to be able to show you more examples of the SRL16E in 
      action. We have seen the SRL16E used in dynamic addressing mode to act as 
      a very efficient bit re-ordering circuit, as well as to provide pure 
      delay. Serial processing really can be quite tricky to implement, but with 
      the SRL16E's ability to provide a complementary state machine with direct 
      control over the scheduling of events, then this is really so much easier 
      and smaller than it has been in the past using counters. The serial 
      implementation requires a total of just 6 "slices" to implement the 14-bit 
      serial DC offset removal circuit and means that even the smallest XC2S15 
      device could support 32 channels.</P>
      <P>As a last thought, I would like you to consider that for an 8kHz sample 
      rate, this serial process will only require a minimum clock rate of 
      176kHz. Given that a Spartan-II can easily support 100MHz clock rates, 
      just one serial processing circuit could actually support 568 channels 
      using time division multiplexing (TDM) techniques. In this situation, the 
      amount of memory required to store the DC levels (accumulator values) 
      would be better supported by 3 block RAMs, each acting as 4096-bit serial 
      cyclic buffers.</P>
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