lab.stx

Manual for DSP sp3 for students who do coding

Release 8.2i - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
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=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "lab.v" in library verilog
Module <lab> compiled
No errors in compilation
Analysis of file <"lab.prj"> succeeded.
 
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Total memory usage is 108196 kilobytes

Number of errors   :    0 (   0 filtered)
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Number of infos    :    0 (   0 filtered)