lab.syr

Manual for DSP sp3 for students who do coding

Release 8.2i - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
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--> Reading design: lab.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "lab.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "lab"
Output Format                      : NGC
Target Device                      : xc4vlx100-12-ff1148

---- Source Options
Top Module Name                    : lab
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 32
Number of Regional Clock Buffers   : 48
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
DSP48 Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : lab.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
use_dsp48                          : auto
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Auto
use_sync_set                       : Auto
use_sync_reset                     : Auto

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "lab.v" in library verilog
Module <lab> compiled
No errors in compilation
Analysis of file <"lab.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <lab> in library <verilog>.

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <lab>.
Module <lab> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <lab>.
    Related source file is "lab.v".
WARNING:Xst:737 - Found 1-bit latch for signal <cout>.
WARNING:Xst:737 - Found 1-bit latch for signal <sum>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0000>.
    Summary:
	inferred   1 Multiplexer(s).
Unit <lab> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Latches                                              : 2
 1-bit latch                                           : 2
# Multiplexers                                         : 1
 1-bit 4-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '4vlx100.nph' in environment C:\Xilinx.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Latches                                              : 2
 1-bit latch                                           : 2
# Multiplexers                                         : 1
 1-bit 4-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <lab> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lab, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : lab.ngr
Top Level Output File Name         : lab
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 5

Cell Usage :
# BELS                             : 5
#      GND                         : 1
#      LUT2                        : 1
#      LUT3                        : 3
# FlipFlops/Latches                : 2
#      LD                          : 1
#      LDP                         : 1
# IO Buffers                       : 5
#      IBUF                        : 3
#      OBUF                        : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 4vlx100ff1148-12 

 Number of Slices:                       2  out of  49152     0%  
 Number of Slice Flip Flops:             2  out of  98304     0%  
 Number of 4 input LUTs:                 4  out of  98304     0%  
 Number of IOs:                          5
 Number of bonded IOBs:                  5  out of    768     0%  
    IOB Flip Flops:                      2


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_not0001(_not00011:O)              | NONE(*)(sum)           | 1     |
_or0000(_or00001:O)                | NONE(*)(cout)          | 1     |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
_or0001(_or00011:O)                | NONE(cout)             | 1     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -12

   Minimum period: No path found
   Minimum input arrival time before clock: 1.779ns
   Maximum output required time after clock: 4.007ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock '_not0001'
  Total number of paths / destination ports: 3 / 1
-------------------------------------------------------------------------
Offset:              1.779ns (Levels of Logic = 2)
  Source:            cin (PAD)
  Destination:       sum (LATCH)
  Destination Clock: _not0001 falling

  Data Path: cin to sum
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   0.754   0.581  cin_IBUF (cin_IBUF)
     LUT3:I0->O            1   0.147   0.000  _mux00001 (_mux0000)
     LD:D                      0.297          sum
    ----------------------------------------
    Total                      1.779ns (1.198ns logic, 0.581ns route)
                                       (67.3% logic, 32.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock '_or0000'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              4.007ns (Levels of Logic = 1)
  Source:            cout (LATCH)
  Destination:       cout (PAD)
  Source Clock:      _or0000 falling

  Data Path: cout to cout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDP:G->Q              1   0.358   0.394  cout (cout_OBUF)
     OBUF:I->O                 3.255          cout_OBUF (cout)
    ----------------------------------------
    Total                      4.007ns (3.613ns logic, 0.394ns route)
                                       (90.2% logic, 9.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock '_not0001'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              4.007ns (Levels of Logic = 1)
  Source:            sum (LATCH)
  Destination:       sum (PAD)
  Source Clock:      _not0001 falling

  Data Path: sum to sum
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.358   0.394  sum (sum_OBUF)
     OBUF:I->O                 3.255          sum_OBUF (sum)
    ----------------------------------------
    Total                      4.007ns (3.613ns logic, 0.394ns route)
                                       (90.2% logic, 9.8% route)

=========================================================================
CPU : 12.64 / 13.03 s | Elapsed : 12.00 / 13.00 s
 
--> 

Total memory usage is 328464 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    2 (   0 filtered)