📄 6_bit.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:33:36 01/21/2009
// Design Name:
// Module Name: 6bitadder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module 6bitadder(cin,a[5:0],b[5:0],cout,sum[5:0]);
input cin;
input a[5:0];
input b[5:0];
output sum[5:0];
output cout;
reg sum[5:0] , cout;
wire ctemp[4:0];
labfirst l1(cin,a[0],b[0],sum[0],ctemp[0]);
labfirst l2(ctemp[0],a[1],b[1],sum[1],ctemp[1]);
labfirst l3(ctemp[1],a[2],b[2],sum[2],ctemp[2]);
labfirst l4(ctemp[2],a[3],b[3],sum[3],ctemp[3]);
labfirst l5(ctemp[3],a[4],b[4],sum[4],ctemp[4]);
labfirst l6(ctemp[4],a[5],b[5],sum[5],cout);
endmodule
module labfirst(cin, a, b, sum, cout);
input cin;
input a;
input b;
output sum;
output cout;
reg sum , cout;
always @ (cin , a , b) begin
if (a == 1 && b == 1 && cin == 1) begin
sum = 1 ;
cout = 1;
end
else if (a == 1 && b == 1 && cin == 0) begin
sum = 0 ;
cout = 1;
end
else if (a == 1 && b == 0 && cin == 0) begin
sum = 1 ;
cout = 0;
end
else if (a == 1 && b == 0 && cin == 1) begin
sum = 0 ;
cout = 1;
end
else if (a == 0 && b == 1 && cin == 0) begin
sum = 1 ;
cout = 0;
end
else if (a == 0 && b == 1 && cin == 1) begin
sum = 0 ;
cout = 1;
end
else if (a == 0 && b == 0 && cin == 1) begin
sum = 1 ;
cout = 0;
end
else if (a == 0 && b == 0 && cin == 0) begin
sum = 0 ;
cout = 0;
end
end
endmodule
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