lab.v

来自「Manual for DSP sp3 for students who do c」· Verilog 代码 · 共 54 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:54:15 01/21/2009 
// Design Name: 
// Module Name:    lab 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module lab(cin, a, b, sum, cout);
    input cin;
    input a;
    input b;
    output sum;
    output cout;
	 reg sum , cout;
	 
	 always @ (cin , a , b) begin
	 
	 if (a == 1 && b == 1 && cin == 1) begin 
		sum = 1 ;
		cout = 1;
		end 
	 
	 else if ((a == 1 || b == 1) && cin == 1) begin 
		sum = 0 ;
		cout = 1;
		end 
	
	else if (a == 0 && b == 0 && cin == 1) begin 
		sum = 1 ;
		cout = 0;
		end 
		
		else if (a == 0 && b == 0 && cin == 0) begin 
		sum = 0 ;
		cout = 0;
		end 

		end

endmodule