test6bit.v

来自「Manual for DSP sp3 for students who do c」· Verilog 代码 · 共 48 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:53:29 01/21/2009 
// Design Name: 
// Module Name:    test6bit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module test6bit();

wire [5:0] sum;
wire cout;
reg cin;
reg [5:0] a;
reg [5:0] b;

tt t1(cin, a[5:0], b[5:0], cout, sum[5:0]);

initial begin


a=6'b000001;
cin=1;
b=6'b010000;
#5;
a=6'b000100;
cin=0;
b=6'b010000;
#5;
a=6'b100001;
cin=1;
b=6'b010000;
#5;
end
endmodule