system.h

NIOSII的液晶显示ip 核

/* system.h
 *
 * Machine generated for a CPU named "cpu" as defined in:
 * d:\GX_SOPC_Dev_Lab\EP2C35\projects\M4\software\std_2c35_syslib\..\..\NiosII_cycloneII_2c35_standard_sopc.ptf
 *
 * Generated: 2008-11-30 10:24:29.234
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "NiosII_cycloneII_2c35_standard_sopc"
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONEII"
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN_BASE 0x02409840
#define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_PRESENT
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT_BASE 0x02409840
#define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_PRESENT
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDERR_BASE 0x02409840
#define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_PRESENT
#define ALT_CPU_FREQ 50000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_BIG_ENDIAN 0

#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_DCACHE_SIZE 2048
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 32
#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x02404020
#define NIOS2_RESET_ADDR 0x01000000
#define NIOS2_BREAK_ADDR 0x02408820

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_TRI_STATE_BRIDGE
#define __ALTERA_AVALON_CY7C1380_SSRAM
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_CFI_FLASH
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ANYWHERE_AVALON_BITBLT
#define __ANYWHERE_LCD_CONTROLLER
#define __ALTERA_AVALON_SYSID

/*
 * ext_ssram_bus configuration
 *
 */

#define EXT_SSRAM_BUS_NAME "/dev/ext_ssram_bus"
#define EXT_SSRAM_BUS_TYPE "altera_avalon_tri_state_bridge"
#define ALT_MODULE_CLASS_ext_ssram_bus altera_avalon_tri_state_bridge

/*
 * ext_ssram configuration
 *
 */

#define EXT_SSRAM_NAME "/dev/ext_ssram"
#define EXT_SSRAM_TYPE "altera_avalon_cy7c1380_ssram"
#define EXT_SSRAM_BASE 0x02200000
#define EXT_SSRAM_SPAN 2097152
#define EXT_SSRAM_SRAM_MEMORY_SIZE 2
#define EXT_SSRAM_SRAM_MEMORY_UNITS 1048576
#define EXT_SSRAM_SSRAM_DATA_WIDTH 32
#define EXT_SSRAM_SSRAM_READ_LATENCY 2
#define EXT_SSRAM_SIMULATION_MODEL_NUM_LANES 4
#define ALT_MODULE_CLASS_ext_ssram altera_avalon_cy7c1380_ssram

/*
 * jtag_uart configuration
 *
 */

#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x02409840
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 0
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0
#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart

/*
 * ext_flash configuration
 *
 */

#define EXT_FLASH_NAME "/dev/ext_flash"
#define EXT_FLASH_TYPE "altera_avalon_cfi_flash"
#define EXT_FLASH_BASE 0x01000000
#define EXT_FLASH_SPAN 16777216
#define EXT_FLASH_SETUP_VALUE 45
#define EXT_FLASH_WAIT_VALUE 160
#define EXT_FLASH_HOLD_VALUE 35
#define EXT_FLASH_TIMING_UNITS "ns"
#define EXT_FLASH_UNIT_MULTIPLIER 1
#define EXT_FLASH_SIZE 16777216
#define ALT_MODULE_CLASS_ext_flash altera_avalon_cfi_flash

/*
 * ext_flash_bus configuration
 *
 */

#define EXT_FLASH_BUS_NAME "/dev/ext_flash_bus"
#define EXT_FLASH_BUS_TYPE "altera_avalon_tri_state_bridge"
#define ALT_MODULE_CLASS_ext_flash_bus altera_avalon_tri_state_bridge

/*
 * onchip_ram configuration
 *
 */

#define ONCHIP_RAM_NAME "/dev/onchip_ram"
#define ONCHIP_RAM_TYPE "altera_avalon_onchip_memory2"
#define ONCHIP_RAM_BASE 0x02404000
#define ONCHIP_RAM_SPAN 16384
#define ONCHIP_RAM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_RAM_RAM_BLOCK_TYPE "M4K"
#define ONCHIP_RAM_INIT_CONTENTS_FILE "onchip_ram"
#define ONCHIP_RAM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ONCHIP_RAM_GUI_RAM_BLOCK_TYPE "Automatic"
#define ONCHIP_RAM_WRITEABLE 1
#define ONCHIP_RAM_DUAL_PORT 0
#define ONCHIP_RAM_SIZE_VALUE 16384
#define ONCHIP_RAM_SIZE_MULTIPLE 1
#define ONCHIP_RAM_USE_SHALLOW_MEM_BLOCKS 0
#define ONCHIP_RAM_INIT_MEM_CONTENT 1
#define ONCHIP_RAM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ONCHIP_RAM_INSTANCE_ID "NONE"
#define ONCHIP_RAM_READ_DURING_WRITE_MODE "DONT_CARE"
#define ONCHIP_RAM_IGNORE_AUTO_BLOCK_TYPE_ASSIGNMENT 1
#define ONCHIP_RAM_CONTENTS_INFO ""
#define ALT_MODULE_CLASS_onchip_ram altera_avalon_onchip_memory2

/*
 * bitblt configuration
 *
 */

#define BITBLT_NAME "/dev/bitblt"
#define BITBLT_TYPE "anywhere_avalon_bitblt"
#define BITBLT_BASE 0x02409800
#define BITBLT_SPAN 64
#define BITBLT_TERMINATED_PORTS ""
#define ALT_MODULE_CLASS_bitblt anywhere_avalon_bitblt

/*
 * lcd_controller configuration
 *
 */

#define LCD_CONTROLLER_NAME "/dev/lcd_controller"
#define LCD_CONTROLLER_TYPE "anywhere_lcd_controller"
#define LCD_CONTROLLER_BASE 0x02409400
#define LCD_CONTROLLER_SPAN 1024
#define LCD_CONTROLLER_TERMINATED_PORTS ""
#define ALT_MODULE_CLASS_lcd_controller anywhere_lcd_controller

/*
 * sysid configuration
 *
 */

#define SYSID_NAME "/dev/sysid"
#define SYSID_TYPE "altera_avalon_sysid"
#define SYSID_BASE 0x02409848
#define SYSID_SPAN 8
#define SYSID_ID 74899737u
#define SYSID_TIMESTAMP 1228011046u
#define SYSID_REGENERATE_VALUES 0
#define ALT_MODULE_CLASS_sysid altera_avalon_sysid

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK none
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       ONCHIP_RAM
#define ALT_RODATA_DEVICE     ONCHIP_RAM
#define ALT_RWDATA_DEVICE     ONCHIP_RAM
#define ALT_EXCEPTIONS_DEVICE ONCHIP_RAM
#define ALT_RESET_DEVICE      EXT_FLASH


#endif /* __SYSTEM_H_ */