system.h

NIOSII的经典JTAG通信程序,含所有底层源代码

#define LCD_IRQ_NAME "/dev/lcd_IRQ"
#define LCD_IRQ_TYPE "altera_avalon_pio"
#define LCD_IRQ_BASE 0x018808F0
#define LCD_IRQ_SPAN 16
#define LCD_IRQ_DO_TEST_BENCH_WIRING 0
#define LCD_IRQ_DRIVEN_SIM_VALUE 0x0000
#define LCD_IRQ_HAS_TRI 1
#define LCD_IRQ_HAS_OUT 0
#define LCD_IRQ_HAS_IN 0
#define LCD_IRQ_CAPTURE 0
#define LCD_IRQ_EDGE_TYPE "NONE"
#define LCD_IRQ_IRQ_TYPE "NONE"
#define LCD_IRQ_FREQ 12000000
#define ALT_MODULE_CLASS_lcd_IRQ altera_avalon_pio

/*
 * lcd_nWR configuration
 *
 */

#define LCD_NWR_NAME "/dev/lcd_nWR"
#define LCD_NWR_TYPE "altera_avalon_pio"
#define LCD_NWR_BASE 0x01880900
#define LCD_NWR_SPAN 16
#define LCD_NWR_DO_TEST_BENCH_WIRING 0
#define LCD_NWR_DRIVEN_SIM_VALUE 0x0000
#define LCD_NWR_HAS_TRI 1
#define LCD_NWR_HAS_OUT 0
#define LCD_NWR_HAS_IN 0
#define LCD_NWR_CAPTURE 0
#define LCD_NWR_EDGE_TYPE "NONE"
#define LCD_NWR_IRQ_TYPE "NONE"
#define LCD_NWR_FREQ 12000000
#define ALT_MODULE_CLASS_lcd_nWR altera_avalon_pio

/*
 * lcd_nCS configuration
 *
 */

#define LCD_NCS_NAME "/dev/lcd_nCS"
#define LCD_NCS_TYPE "altera_avalon_pio"
#define LCD_NCS_BASE 0x01880910
#define LCD_NCS_SPAN 16
#define LCD_NCS_DO_TEST_BENCH_WIRING 0
#define LCD_NCS_DRIVEN_SIM_VALUE 0x0000
#define LCD_NCS_HAS_TRI 1
#define LCD_NCS_HAS_OUT 0
#define LCD_NCS_HAS_IN 0
#define LCD_NCS_CAPTURE 0
#define LCD_NCS_EDGE_TYPE "NONE"
#define LCD_NCS_IRQ_TYPE "NONE"
#define LCD_NCS_FREQ 12000000
#define ALT_MODULE_CLASS_lcd_nCS altera_avalon_pio

/*
 * lcd_nRD configuration
 *
 */

#define LCD_NRD_NAME "/dev/lcd_nRD"
#define LCD_NRD_TYPE "altera_avalon_pio"
#define LCD_NRD_BASE 0x01880920
#define LCD_NRD_SPAN 16
#define LCD_NRD_DO_TEST_BENCH_WIRING 0
#define LCD_NRD_DRIVEN_SIM_VALUE 0x0000
#define LCD_NRD_HAS_TRI 1
#define LCD_NRD_HAS_OUT 0
#define LCD_NRD_HAS_IN 0
#define LCD_NRD_CAPTURE 0
#define LCD_NRD_EDGE_TYPE "NONE"
#define LCD_NRD_IRQ_TYPE "NONE"
#define LCD_NRD_FREQ 12000000
#define ALT_MODULE_CLASS_lcd_nRD altera_avalon_pio

/*
 * spi_adc_cs configuration
 *
 */

#define SPI_ADC_CS_NAME "/dev/spi_adc_cs"
#define SPI_ADC_CS_TYPE "altera_avalon_pio"
#define SPI_ADC_CS_BASE 0x01880930
#define SPI_ADC_CS_SPAN 16
#define SPI_ADC_CS_DO_TEST_BENCH_WIRING 0
#define SPI_ADC_CS_DRIVEN_SIM_VALUE 0x0000
#define SPI_ADC_CS_HAS_TRI 0
#define SPI_ADC_CS_HAS_OUT 1
#define SPI_ADC_CS_HAS_IN 0
#define SPI_ADC_CS_CAPTURE 0
#define SPI_ADC_CS_EDGE_TYPE "NONE"
#define SPI_ADC_CS_IRQ_TYPE "NONE"
#define SPI_ADC_CS_FREQ 50000000
#define ALT_MODULE_CLASS_spi_adc_cs altera_avalon_pio

/*
 * spi_adc_sclk configuration
 *
 */

#define SPI_ADC_SCLK_NAME "/dev/spi_adc_sclk"
#define SPI_ADC_SCLK_TYPE "altera_avalon_pio"
#define SPI_ADC_SCLK_BASE 0x01880940
#define SPI_ADC_SCLK_SPAN 16
#define SPI_ADC_SCLK_DO_TEST_BENCH_WIRING 0
#define SPI_ADC_SCLK_DRIVEN_SIM_VALUE 0x0000
#define SPI_ADC_SCLK_HAS_TRI 0
#define SPI_ADC_SCLK_HAS_OUT 1
#define SPI_ADC_SCLK_HAS_IN 0
#define SPI_ADC_SCLK_CAPTURE 0
#define SPI_ADC_SCLK_EDGE_TYPE "NONE"
#define SPI_ADC_SCLK_IRQ_TYPE "NONE"
#define SPI_ADC_SCLK_FREQ 50000000
#define ALT_MODULE_CLASS_spi_adc_sclk altera_avalon_pio

/*
 * spi_adc_sdata configuration
 *
 */

#define SPI_ADC_SDATA_NAME "/dev/spi_adc_sdata"
#define SPI_ADC_SDATA_TYPE "altera_avalon_pio"
#define SPI_ADC_SDATA_BASE 0x01880950
#define SPI_ADC_SDATA_SPAN 16
#define SPI_ADC_SDATA_DO_TEST_BENCH_WIRING 0
#define SPI_ADC_SDATA_DRIVEN_SIM_VALUE 0x0000
#define SPI_ADC_SDATA_HAS_TRI 0
#define SPI_ADC_SDATA_HAS_OUT 0
#define SPI_ADC_SDATA_HAS_IN 1
#define SPI_ADC_SDATA_CAPTURE 0
#define SPI_ADC_SDATA_EDGE_TYPE "NONE"
#define SPI_ADC_SDATA_IRQ_TYPE "NONE"
#define SPI_ADC_SDATA_FREQ 50000000
#define ALT_MODULE_CLASS_spi_adc_sdata altera_avalon_pio

/*
 * spi_dac_clk configuration
 *
 */

#define SPI_DAC_CLK_NAME "/dev/spi_dac_clk"
#define SPI_DAC_CLK_TYPE "altera_avalon_pio"
#define SPI_DAC_CLK_BASE 0x01880960
#define SPI_DAC_CLK_SPAN 16
#define SPI_DAC_CLK_DO_TEST_BENCH_WIRING 0
#define SPI_DAC_CLK_DRIVEN_SIM_VALUE 0x0000
#define SPI_DAC_CLK_HAS_TRI 0
#define SPI_DAC_CLK_HAS_OUT 1
#define SPI_DAC_CLK_HAS_IN 0
#define SPI_DAC_CLK_CAPTURE 0
#define SPI_DAC_CLK_EDGE_TYPE "NONE"
#define SPI_DAC_CLK_IRQ_TYPE "NONE"
#define SPI_DAC_CLK_FREQ 50000000
#define ALT_MODULE_CLASS_spi_dac_clk altera_avalon_pio

/*
 * spi_dac_data configuration
 *
 */

#define SPI_DAC_DATA_NAME "/dev/spi_dac_data"
#define SPI_DAC_DATA_TYPE "altera_avalon_pio"
#define SPI_DAC_DATA_BASE 0x01880970
#define SPI_DAC_DATA_SPAN 16
#define SPI_DAC_DATA_DO_TEST_BENCH_WIRING 0
#define SPI_DAC_DATA_DRIVEN_SIM_VALUE 0x0000
#define SPI_DAC_DATA_HAS_TRI 0
#define SPI_DAC_DATA_HAS_OUT 1
#define SPI_DAC_DATA_HAS_IN 0
#define SPI_DAC_DATA_CAPTURE 0
#define SPI_DAC_DATA_EDGE_TYPE "NONE"
#define SPI_DAC_DATA_IRQ_TYPE "NONE"
#define SPI_DAC_DATA_FREQ 50000000
#define ALT_MODULE_CLASS_spi_dac_data altera_avalon_pio

/*
 * spi_dac_ldac configuration
 *
 */

#define SPI_DAC_LDAC_NAME "/dev/spi_dac_ldac"
#define SPI_DAC_LDAC_TYPE "altera_avalon_pio"
#define SPI_DAC_LDAC_BASE 0x01880980
#define SPI_DAC_LDAC_SPAN 16
#define SPI_DAC_LDAC_DO_TEST_BENCH_WIRING 0
#define SPI_DAC_LDAC_DRIVEN_SIM_VALUE 0x0000
#define SPI_DAC_LDAC_HAS_TRI 0
#define SPI_DAC_LDAC_HAS_OUT 1
#define SPI_DAC_LDAC_HAS_IN 0
#define SPI_DAC_LDAC_CAPTURE 0
#define SPI_DAC_LDAC_EDGE_TYPE "NONE"
#define SPI_DAC_LDAC_IRQ_TYPE "NONE"
#define SPI_DAC_LDAC_FREQ 50000000
#define ALT_MODULE_CLASS_spi_dac_ldac altera_avalon_pio

/*
 * spi_dac_load configuration
 *
 */

#define SPI_DAC_LOAD_NAME "/dev/spi_dac_load"
#define SPI_DAC_LOAD_TYPE "altera_avalon_pio"
#define SPI_DAC_LOAD_BASE 0x01880990
#define SPI_DAC_LOAD_SPAN 16
#define SPI_DAC_LOAD_DO_TEST_BENCH_WIRING 0
#define SPI_DAC_LOAD_DRIVEN_SIM_VALUE 0x0000
#define SPI_DAC_LOAD_HAS_TRI 0
#define SPI_DAC_LOAD_HAS_OUT 1
#define SPI_DAC_LOAD_HAS_IN 0
#define SPI_DAC_LOAD_CAPTURE 0
#define SPI_DAC_LOAD_EDGE_TYPE "NONE"
#define SPI_DAC_LOAD_IRQ_TYPE "NONE"
#define SPI_DAC_LOAD_FREQ 50000000
#define ALT_MODULE_CLASS_spi_dac_load altera_avalon_pio

/*
 * i2c_sda configuration
 *
 */

#define I2C_SDA_NAME "/dev/i2c_sda"
#define I2C_SDA_TYPE "altera_avalon_pio"
#define I2C_SDA_BASE 0x018809A0
#define I2C_SDA_SPAN 16
#define I2C_SDA_DO_TEST_BENCH_WIRING 0
#define I2C_SDA_DRIVEN_SIM_VALUE 0x0000
#define I2C_SDA_HAS_TRI 1
#define I2C_SDA_HAS_OUT 0
#define I2C_SDA_HAS_IN 0
#define I2C_SDA_CAPTURE 0
#define I2C_SDA_EDGE_TYPE "NONE"
#define I2C_SDA_IRQ_TYPE "NONE"
#define I2C_SDA_FREQ 50000000
#define ALT_MODULE_CLASS_i2c_sda altera_avalon_pio

/*
 * i2c_scl configuration
 *
 */

#define I2C_SCL_NAME "/dev/i2c_scl"
#define I2C_SCL_TYPE "altera_avalon_pio"
#define I2C_SCL_BASE 0x018809B0
#define I2C_SCL_SPAN 16
#define I2C_SCL_DO_TEST_BENCH_WIRING 0
#define I2C_SCL_DRIVEN_SIM_VALUE 0x0000
#define I2C_SCL_HAS_TRI 0
#define I2C_SCL_HAS_OUT 1
#define I2C_SCL_HAS_IN 0
#define I2C_SCL_CAPTURE 0
#define I2C_SCL_EDGE_TYPE "NONE"
#define I2C_SCL_IRQ_TYPE "NONE"
#define I2C_SCL_FREQ 50000000
#define ALT_MODULE_CLASS_i2c_scl altera_avalon_pio

/*
 * sysid configuration
 *
 */

#define SYSID_NAME "/dev/sysid"
#define SYSID_TYPE "altera_avalon_sysid"
#define SYSID_BASE 0x018809D8
#define SYSID_SPAN 8
#define SYSID_ID 3862097128u
#define SYSID_TIMESTAMP 1183710170u
#define ALT_MODULE_CLASS_sysid altera_avalon_sysid

/*
 * sys_clock_timer configuration
 *
 */

#define SYS_CLOCK_TIMER_NAME "/dev/sys_clock_timer"
#define SYS_CLOCK_TIMER_TYPE "altera_avalon_timer"
#define SYS_CLOCK_TIMER_BASE 0x01880820
#define SYS_CLOCK_TIMER_SPAN 32
#define SYS_CLOCK_TIMER_IRQ 4
#define SYS_CLOCK_TIMER_ALWAYS_RUN 0
#define SYS_CLOCK_TIMER_FIXED_PERIOD 0
#define SYS_CLOCK_TIMER_SNAPSHOT 1
#define SYS_CLOCK_TIMER_PERIOD 20
#define SYS_CLOCK_TIMER_PERIOD_UNITS "ms"
#define SYS_CLOCK_TIMER_RESET_OUTPUT 0
#define SYS_CLOCK_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define SYS_CLOCK_TIMER_MULT 0.001
#define SYS_CLOCK_TIMER_COUNTER_SIZE 32
#define SYS_CLOCK_TIMER_FREQ 50000000
#define ALT_MODULE_CLASS_sys_clock_timer altera_avalon_timer

/*
 * highres_timer configuration
 *
 */

#define HIGHRES_TIMER_NAME "/dev/highres_timer"
#define HIGHRES_TIMER_TYPE "altera_avalon_timer"
#define HIGHRES_TIMER_BASE 0x01880840
#define HIGHRES_TIMER_SPAN 32
#define HIGHRES_TIMER_IRQ 5
#define HIGHRES_TIMER_ALWAYS_RUN 0
#define HIGHRES_TIMER_FIXED_PERIOD 0
#define HIGHRES_TIMER_SNAPSHOT 1
#define HIGHRES_TIMER_PERIOD 1
#define HIGHRES_TIMER_PERIOD_UNITS "ms"
#define HIGHRES_TIMER_RESET_OUTPUT 0
#define HIGHRES_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define HIGHRES_TIMER_MULT 0.001
#define HIGHRES_TIMER_COUNTER_SIZE 32
#define HIGHRES_TIMER_FREQ 50000000
#define ALT_MODULE_CLASS_highres_timer altera_avalon_timer

/*
 * watchdog configuration
 *
 */

#define WATCHDOG_NAME "/dev/watchdog"
#define WATCHDOG_TYPE "altera_avalon_timer"
#define WATCHDOG_BASE 0x01880860
#define WATCHDOG_SPAN 32
#define WATCHDOG_IRQ 6
#define WATCHDOG_ALWAYS_RUN 1
#define WATCHDOG_FIXED_PERIOD 1
#define WATCHDOG_SNAPSHOT 0
#define WATCHDOG_PERIOD 1
#define WATCHDOG_PERIOD_UNITS "ms"
#define WATCHDOG_RESET_OUTPUT 1
#define WATCHDOG_TIMEOUT_PULSE_OUTPUT 0
#define WATCHDOG_MULT 0.001
#define WATCHDOG_COUNTER_SIZE 32
#define WATCHDOG_FREQ 50000000
#define ALT_MODULE_CLASS_watchdog altera_avalon_timer

/*
 * lcd_16207 configuration
 *
 */

#define LCD_16207_NAME "/dev/lcd_16207"
#define LCD_16207_TYPE "altera_avalon_lcd_16207"
#define LCD_16207_BASE 0x018809C0
#define LCD_16207_SPAN 16
#define ALT_MODULE_CLASS_lcd_16207 altera_avalon_lcd_16207

/*
 * dma configuration
 *
 */

#define DMA_NAME "/dev/dma"
#define DMA_TYPE "altera_avalon_dma"
#define DMA_BASE 0x018809E0
#define DMA_SPAN 32
#define DMA_IRQ 7
#define DMA_READADDRESS_RESET_VALUE 0x0
#define DMA_WRITEADDRESS_RESET_VALUE 0x0
#define DMA_LENGTH_RESET_VALUE 0x0
#define DMA_CONTROL_BYTE_RESET_VALUE 0
#define DMA_CONTROL_HW_RESET_VALUE 0
#define DMA_CONTROL_WORD_RESET_VALUE 1
#define DMA_CONTROL_GO_RESET_VALUE 0
#define DMA_CONTROL_I_EN_RESET_VALUE 0
#define DMA_CONTROL_REEN_RESET_VALUE 0
#define DMA_CONTROL_WEEN_RESET_VALUE 0
#define DMA_CONTROL_LEEN_RESET_VALUE 1
#define DMA_CONTROL_RCON_RESET_VALUE 0
#define DMA_CONTROL_WCON_RESET_VALUE 0
#define DMA_CONTROL_DOUBLEWORD_RESET_VALUE 0
#define DMA_CONTROL_QUADWORD_RESET_VALUE 0
#define DMA_CONTROL_SOFTWARERESET_RESET_VALUE 0
#define DMA_LENGTHWIDTH 16
#define DMA_BURST_ENABLE 0
#define DMA_FIFO_IN_LOGIC_ELEMENTS 1
#define DMA_ALLOW_BYTE_TRANSACTIONS 1
#define DMA_ALLOW_HW_TRANSACTIONS 1
#define DMA_ALLOW_WORD_TRANSACTIONS 1
#define DMA_ALLOW_DOUBLEWORD_TRANSACTIONS 1
#define DMA_ALLOW_QUADWORD_TRANSACTIONS 1
#define DMA_MAX_BURST_SIZE 128
#define DMA_BIG_ENDIAN 0
#define DMA_ALTERA_SHOW_UNPUBLISHED_FEATURES 0
#define ALT_MODULE_CLASS_dma altera_avalon_dma

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK SYS_CLOCK_TIMER
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SRAM
#define ALT_RODATA_DEVICE     SRAM
#define ALT_RWDATA_DEVICE     SRAM
#define ALT_EXCEPTIONS_DEVICE SDRAM
#define ALT_RESET_DEVICE      FLASH


#endif /* __SYSTEM_H_ */