system.h

NIOSII的经典JTAG通信程序,含所有底层源代码

/* system.h
 *
 * Machine generated for a CPU named "cpu" as defined in:
 * d:\M1\software\hello_world_syslib\..\..\std_2c50_M1.ptf
 *
 * Generated: 2009-03-26 21:00:03.656
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "std_2c50_M1"
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONEII"
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN_BASE 0x018809D0
#define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_PRESENT
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT_BASE 0x018809D0
#define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_PRESENT
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDERR_BASE 0x018809D0
#define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_PRESENT
#define ALT_CPU_FREQ 50000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "small"
#define NIOS2_BIG_ENDIAN 0

#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x01000020
#define NIOS2_RESET_ADDR 0x00000000
#define NIOS2_BREAK_ADDR 0x01880020

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_TRI_STATE_BRIDGE
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_UART
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __SRAM_256X16BIT
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_CFI_FLASH
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SYSID
#define __ALTERA_AVALON_TIMER
#define __ALTERA_AVALON_LCD_16207
#define __ALTERA_AVALON_DMA

/*
 * ext_bus configuration
 *
 */

#define EXT_BUS_NAME "/dev/ext_bus"
#define EXT_BUS_TYPE "altera_avalon_tri_state_bridge"
#define ALT_MODULE_CLASS_ext_bus altera_avalon_tri_state_bridge

/*
 * jtag_uart configuration
 *
 */

#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x018809D0
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 0
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0
#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart

/*
 * uart_rs232 configuration
 *
 */

#define UART_RS232_NAME "/dev/uart_rs232"
#define UART_RS232_TYPE "altera_avalon_uart"
#define UART_RS232_BASE 0x01880800
#define UART_RS232_SPAN 32
#define UART_RS232_IRQ 1
#define UART_RS232_BAUD 115200
#define UART_RS232_DATA_BITS 8
#define UART_RS232_FIXED_BAUD 1
#define UART_RS232_PARITY 'N'
#define UART_RS232_STOP_BITS 1
#define UART_RS232_USE_CTS_RTS 0
#define UART_RS232_USE_EOP_REGISTER 1
#define UART_RS232_SIM_TRUE_BAUD 0
#define UART_RS232_SIM_CHAR_STREAM ""
#define UART_RS232_FREQ 50000000
#define ALT_MODULE_CLASS_uart_rs232 altera_avalon_uart

/*
 * sdram configuration
 *
 */

#define SDRAM_NAME "/dev/sdram"
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_BASE 0x01000000
#define SDRAM_SPAN 8388608
#define SDRAM_REGISTER_DATA_IN 1
#define SDRAM_SIM_MODEL_BASE 1
#define SDRAM_SDRAM_DATA_WIDTH 16
#define SDRAM_SDRAM_ADDR_WIDTH 12
#define SDRAM_SDRAM_ROW_WIDTH 12
#define SDRAM_SDRAM_COL_WIDTH 8
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_SDRAM_NUM_BANKS 4
#define SDRAM_REFRESH_PERIOD 15.625
#define SDRAM_POWERUP_DELAY 100
#define SDRAM_CAS_LATENCY 3
#define SDRAM_T_RFC 70
#define SDRAM_T_RP 20
#define SDRAM_T_MRD 3
#define SDRAM_T_RCD 20
#define SDRAM_T_AC 5.5
#define SDRAM_T_WR 14
#define SDRAM_INIT_REFRESH_COMMANDS 2
#define SDRAM_INIT_NOP_DELAY 0
#define SDRAM_SHARED_DATA 0
#define SDRAM_STARVATION_INDICATOR 0
#define SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_IS_INITIALIZED 1
#define SDRAM_SDRAM_BANK_WIDTH 2
#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller

/*
 * sram configuration
 *
 */

#define SRAM_NAME "/dev/sram"
#define SRAM_TYPE "sram_256x16bit"
#define SRAM_BASE 0x01800000
#define SRAM_SPAN 524288
#define ALT_MODULE_CLASS_sram sram_256x16bit

/*
 * onchip_ram configuration
 *
 */

#define ONCHIP_RAM_NAME "/dev/onchip_ram"
#define ONCHIP_RAM_TYPE "altera_avalon_onchip_memory2"
#define ONCHIP_RAM_BASE 0x01881000
#define ONCHIP_RAM_SPAN 2048
#define ONCHIP_RAM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_RAM_RAM_BLOCK_TYPE "M4K"
#define ONCHIP_RAM_INIT_CONTENTS_FILE "onchip_ram"
#define ONCHIP_RAM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ONCHIP_RAM_GUI_RAM_BLOCK_TYPE "Automatic"
#define ONCHIP_RAM_WRITEABLE 1
#define ONCHIP_RAM_DUAL_PORT 0
#define ONCHIP_RAM_SIZE_VALUE 2
#define ONCHIP_RAM_SIZE_MULTIPLE 1024
#define ONCHIP_RAM_CONTENTS_INFO "QUARTUS_PROJECT_DIR/onchip_ram.hex 1183710110"
#define ALT_MODULE_CLASS_onchip_ram altera_avalon_onchip_memory2

/*
 * flash configuration
 *
 */

#define FLASH_NAME "/dev/flash"
#define FLASH_TYPE "altera_avalon_cfi_flash"
#define FLASH_BASE 0x00000000
#define FLASH_SPAN 16777216
#define FLASH_SETUP_VALUE 40
#define FLASH_WAIT_VALUE 160
#define FLASH_HOLD_VALUE 40
#define FLASH_TIMING_UNITS "ns"
#define FLASH_UNIT_MULTIPLIER 1
#define FLASH_SIZE 16777216
#define ALT_MODULE_CLASS_flash altera_avalon_cfi_flash

/*
 * button_pio configuration
 *
 */

#define BUTTON_PIO_NAME "/dev/button_pio"
#define BUTTON_PIO_TYPE "altera_avalon_pio"
#define BUTTON_PIO_BASE 0x01880880
#define BUTTON_PIO_SPAN 16
#define BUTTON_PIO_IRQ 2
#define BUTTON_PIO_DO_TEST_BENCH_WIRING 0
#define BUTTON_PIO_DRIVEN_SIM_VALUE 0x0000
#define BUTTON_PIO_HAS_TRI 0
#define BUTTON_PIO_HAS_OUT 0
#define BUTTON_PIO_HAS_IN 1
#define BUTTON_PIO_CAPTURE 1
#define BUTTON_PIO_EDGE_TYPE "FALLING"
#define BUTTON_PIO_IRQ_TYPE "EDGE"
#define BUTTON_PIO_FREQ 50000000
#define ALT_MODULE_CLASS_button_pio altera_avalon_pio

/*
 * led_pio configuration
 *
 */

#define LED_PIO_NAME "/dev/led_pio"
#define LED_PIO_TYPE "altera_avalon_pio"
#define LED_PIO_BASE 0x01880890
#define LED_PIO_SPAN 16
#define LED_PIO_DO_TEST_BENCH_WIRING 0
#define LED_PIO_DRIVEN_SIM_VALUE 0x0000
#define LED_PIO_HAS_TRI 0
#define LED_PIO_HAS_OUT 1
#define LED_PIO_HAS_IN 0
#define LED_PIO_CAPTURE 0
#define LED_PIO_EDGE_TYPE "NONE"
#define LED_PIO_IRQ_TYPE "NONE"
#define LED_PIO_FREQ 50000000
#define ALT_MODULE_CLASS_led_pio altera_avalon_pio

/*
 * seg_key_scl configuration
 *
 */

#define SEG_KEY_SCL_NAME "/dev/seg_key_scl"
#define SEG_KEY_SCL_TYPE "altera_avalon_pio"
#define SEG_KEY_SCL_BASE 0x018808A0
#define SEG_KEY_SCL_SPAN 16
#define SEG_KEY_SCL_DO_TEST_BENCH_WIRING 0
#define SEG_KEY_SCL_DRIVEN_SIM_VALUE 0x0000
#define SEG_KEY_SCL_HAS_TRI 1
#define SEG_KEY_SCL_HAS_OUT 0
#define SEG_KEY_SCL_HAS_IN 0
#define SEG_KEY_SCL_CAPTURE 0
#define SEG_KEY_SCL_EDGE_TYPE "NONE"
#define SEG_KEY_SCL_IRQ_TYPE "NONE"
#define SEG_KEY_SCL_FREQ 50000000
#define ALT_MODULE_CLASS_seg_key_scl altera_avalon_pio

/*
 * seg_key_sda configuration
 *
 */

#define SEG_KEY_SDA_NAME "/dev/seg_key_sda"
#define SEG_KEY_SDA_TYPE "altera_avalon_pio"
#define SEG_KEY_SDA_BASE 0x018808B0
#define SEG_KEY_SDA_SPAN 16
#define SEG_KEY_SDA_DO_TEST_BENCH_WIRING 0
#define SEG_KEY_SDA_DRIVEN_SIM_VALUE 0x0000
#define SEG_KEY_SDA_HAS_TRI 1
#define SEG_KEY_SDA_HAS_OUT 0
#define SEG_KEY_SDA_HAS_IN 0
#define SEG_KEY_SDA_CAPTURE 0
#define SEG_KEY_SDA_EDGE_TYPE "NONE"
#define SEG_KEY_SDA_IRQ_TYPE "NONE"
#define SEG_KEY_SDA_FREQ 50000000
#define ALT_MODULE_CLASS_seg_key_sda altera_avalon_pio

/*
 * key_INT_n configuration
 *
 */

#define KEY_INT_N_NAME "/dev/key_INT_n"
#define KEY_INT_N_TYPE "altera_avalon_pio"
#define KEY_INT_N_BASE 0x018808C0
#define KEY_INT_N_SPAN 16
#define KEY_INT_N_IRQ 3
#define KEY_INT_N_DO_TEST_BENCH_WIRING 0
#define KEY_INT_N_DRIVEN_SIM_VALUE 0x0000
#define KEY_INT_N_HAS_TRI 0
#define KEY_INT_N_HAS_OUT 0
#define KEY_INT_N_HAS_IN 1
#define KEY_INT_N_CAPTURE 1
#define KEY_INT_N_EDGE_TYPE "FALLING"
#define KEY_INT_N_IRQ_TYPE "EDGE"
#define KEY_INT_N_FREQ 50000000
#define ALT_MODULE_CLASS_key_INT_n altera_avalon_pio

/*
 * lcd_1095_data configuration
 *
 */

#define LCD_1095_DATA_NAME "/dev/lcd_1095_data"
#define LCD_1095_DATA_TYPE "altera_avalon_pio"
#define LCD_1095_DATA_BASE 0x018808D0
#define LCD_1095_DATA_SPAN 16
#define LCD_1095_DATA_DO_TEST_BENCH_WIRING 0
#define LCD_1095_DATA_DRIVEN_SIM_VALUE 0x0000
#define LCD_1095_DATA_HAS_TRI 1
#define LCD_1095_DATA_HAS_OUT 0
#define LCD_1095_DATA_HAS_IN 0
#define LCD_1095_DATA_CAPTURE 0
#define LCD_1095_DATA_EDGE_TYPE "NONE"
#define LCD_1095_DATA_IRQ_TYPE "NONE"
#define LCD_1095_DATA_FREQ 12000000
#define ALT_MODULE_CLASS_lcd_1095_data altera_avalon_pio

/*
 * lcd_RS configuration
 *
 */

#define LCD_RS_NAME "/dev/lcd_RS"
#define LCD_RS_TYPE "altera_avalon_pio"
#define LCD_RS_BASE 0x018808E0
#define LCD_RS_SPAN 16
#define LCD_RS_DO_TEST_BENCH_WIRING 0
#define LCD_RS_DRIVEN_SIM_VALUE 0x0000
#define LCD_RS_HAS_TRI 1
#define LCD_RS_HAS_OUT 0
#define LCD_RS_HAS_IN 0
#define LCD_RS_CAPTURE 0
#define LCD_RS_EDGE_TYPE "NONE"
#define LCD_RS_IRQ_TYPE "NONE"
#define LCD_RS_FREQ 12000000
#define ALT_MODULE_CLASS_lcd_RS altera_avalon_pio

/*
 * lcd_IRQ configuration
 *
 */