fifo123456.txt

16*16位的先进先出队列FIFO程序,可作参考

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fifo16 is
generic (m:positive:=16;
n:positive:=16);
port(rst,clk,wr,rd:in std_logic;
datain:in std_logic_vector((n-1)downto 0);
dataout:out std_logic_vector((n-1)downto 0);
empty,full:std_logic);
end fifo16;

architecture rtl of fifo16 is
type fifo_array is array(0 to(m-1))of bit_vector((n-1)downto 0);
signal fifo_memory:fifo_array;
signal wraddr,rdaddr,offset:natural range 0 to (m-1);
signal rdpulse,wrpulse,q1,q2,q3,q4:std_logic;
signal databuffer:bit_vector((n-1)downto 0);
begin

process
begin
wait until rising_edge(clk);
q1<=wr;
q2<=q1;
q3<=rd;
q4<=q3;
end process;
wrpulse<=q2 and not(q1);
rdpulse<=q4 and not(q3);

fifo_read:process
begin
wait until rising_edge(clk);
if(rst= '1') then
rdaddr<=0;
databuffer<=(others=>'0');
elsif(rdpulse='1'and empty='0') then
databuffer<=fifo_memory(rdaddr);
rdaddr<=rdaddr+1 mod m;
end if;
end process;

fifo_write:process
begin
wait until rising_edge(clk);
if(rst='1') then
wraddr<=0;
elsif(wrpulse='1'and full='0') then
fifo_memory(wraddr)<=to_bitvector(datain);
wraddr<=(wraddr+1) mod m;
end if;
end process;

offset<=(wraddr-rdaddr)when(wraddr>rdaddr);
else(m-(rdaddr-wraddr))when(rdaddr>wraddr);
else 0;
empty<='1'when(offset=0)else '0';
full<='1'when(offset=(m-1))else'0';
dataout<=to_stdlogicvector(databuffer)when(rd='0');
else
(others=>'Z');
end rtl;