demod_tb.vhd

qam的vhdl程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

ENTITY TestDemod IS
END TestDemod;

ARCHITECTURE Bench OF TestDemod IS

  ----------------------------------------------------- UTILITY CONSTANTS ---
  constant ClkPeriod : time := 10 ns;
  constant RstPeriod : time := 50 ns;

  ------------------------------------------------------ SIZING CONSTANTS ---
  constant IF_bits       : integer := 4;
  constant baseband_bits : integer := 8;


  --------------------------------------------- DUT COMPONENT DECLARATION ---
  COMPONENT iq_demod
    GENERIC (
      IF_bits       : natural  := 4;  -- bits of IF, digitised at Clk rate
      baseband_bits : natural  := 8;  -- bit width of I/Q outputs
      -- Numerically controlled oscillator for carrier:
      -- f(carrier) = f(Clk) * carrier_incr / (2**NCO_bits)
      NCO_bits      : positive := 8;  -- bit width of NCO phase accumulator
      carrier_incr  : positive := 32; -- NCO phase increment
      -- Output lowpass filter is a crude single-pole thing, no good!
      filter_shift  : natural  := 4;  -- right shift to scale output filter
      filter_rate   : natural  := 16  -- filter multiplier is rate/2**shift
    );
    PORT (
      Clk, Rst  : in  std_logic;
      IF_signal : in  signed(IF_bits-1 downto 0);
      I, Q      : out signed(baseband_bits-1 downto 0)
    );
  END COMPONENT;

  --------------------------------------------- SIGNALS CONNECTING TO DUT ---
  SIGNAL Clk, Rst   : std_logic;
  SIGNAL IF_signal  : signed(IF_bits-1 downto 0);
  SIGNAL I, Q       : signed(baseband_bits-1 downto 0);

  ---------------------------------------------- SIGNALS DERIVED FROM DUT ---
  SIGNAL RSSI       : real;

  ---------------------------------------------- STIMULUS CONTROL SIGNALS ---
  signal StopTB     : BOOLEAN := FALSE;
  signal SrcI, SrcQ : REAL;
  signal IF_Freq    : REAL := 11.2;  -- 100 MHz * 29/256 = 11.33MHz
  signal SrcData    : Bit_vector(1 downto 0);  -- 0=>I, 1=>Q; '0'=>+, '1'=>-

BEGIN

  ------------------------------------------------------------------- DUT ---
  -- DUT instance
  --
  U1 : iq_demod
          GENERIC MAP (
            IF_bits       =>  4,
            baseband_bits =>  8,
            NCO_bits      =>  8,
            carrier_incr  =>  29,
            filter_shift  =>  2,   -- right shift to scale LP filter
      filter_rate   =>  3
          )
          PORT MAP (
            Clk       => Clk,
            Rst       => Rst,
            IF_signal => IF_signal,
            I         => I,
            Q         => Q
          );

  S_Meter : process (I, Q)
    variable rI, rQ: real;
  begin
    rI := REAL(To_Integer(I));
    rQ := REAL(To_Integer(Q));
    RSSI <= sqrt(rI*rI + rQ*rQ);
  end process;

  ------------------------------------------------------------- UTILITIES ---
  -- Reset generator
  --
  RstGen: Rst <= '1', '0' after RstPeriod;
  --
  -- Clock generator
  --
  ClkGen: process
  begin
    while not StopTB loop
      Clk <= '0', '1' after ClkPeriod/2;
      wait for ClkPeriod;
    end loop;
    wait;
  end process; -- ClkGen


  ------------------------------------------------------------- MODULATOR ---
  -- IF modulator - updates every rise of Clk,
  -- uses SrcI and SrcQ baseband stimulus signals
  -- to calculate appropriate quadrature modulated
  -- signal to apply to IF_Signal
  --
  IF_modulator: process (Clk, IF_Freq)
    -- IF phase angle, in radians
    variable Phase: real := 0.0;
    -- IF frequency, in radians per Clk cycle
    variable IF_Freq_Scale: real;
    -- Internal REAL version of signal output
    variable Real_IF: real;
    -- Scale a real frequency in MHz to real radians per clock period
    constant Freq_To_Scale: real :=
         MATH_2_PI * REAL(ClkPeriod / 1 ps) / REAL(1 us / 1 ps);
  begin
    if rising_edge(Clk) then -- Update phase and IF output
      IF_Freq_Scale := IF_Freq * Freq_To_Scale;
      Phase := (Phase + IF_Freq_Scale) MOD MATH_2_PI;
      Real_IF := SrcI * cos(Phase) + SrcQ * sin(Phase);
      IF_Signal <= to_signed(integer(Real_IF), IF_Signal'LENGTH);
    end if;
  end process; -- IF_modulator


  ----------------------------------------------- BASEBAND COMPLEX CODING ---
  -- Code a data stream into I,Q amplitudes
  --
  Baseband_Coding: process(SrcData'TRANSACTION)
    -- Previous value, to support differential coding
    -- variable Old_SrcData: bit_vector(SrcData'RANGE) := (others => '0');
  begin
    -- Noddy version:  Just code each of two bits on to sign of I, Q
    SrcI <= 4.0;
    if SrcData(0) = '1' then
      SrcI <= -4.0;
    end if;
    SrcQ <= 4.0;
    if SrcData(1) = '1' then
      SrcQ <= -4.0;
    end if;
    -- Old_SrcData := SrcData;
  end process; -- Baseband_Coding

  ------------------------------------------------- TRANSACTION GENERATOR ---

  Data_Gen : process
  begin

    for i in 1 to 10 loop
      SrcData <= "00";
      wait for 1 us;
      SrcData <= "01";
      wait for 1 us;
      SrcData <= "10";
      wait for 1 us;
      SrcData <= "11";
      wait for 1 us;
    end loop;
    -- That's All Folks
    StopTB <= true;
    wait;
  end process; -- DataGen

END Bench;