pn_generator.hier_info

用Verilog编写的一个简单的产生伪随机序列的代码（m序列）

|pn_generator
a[0] => register~13.DATAB
a[1] => register~12.DATAB
a[2] => register~11.DATAB
a[3] => register~10.DATAB
a[4] => register~9.DATAB
a[5] => register~8.DATAB
a[6] => register~7.DATAB
clk => register[6].CLK
clk => register[5].CLK
clk => register[4].CLK
clk => register[3].CLK
clk => register[2].CLK
clk => register[1].CLK
clk => register[0].CLK
clk => counter[7]~reg0.CLK
clk => counter[6]~reg0.CLK
clk => counter[5]~reg0.CLK
clk => counter[4]~reg0.CLK
clk => counter[3]~reg0.CLK
clk => counter[2]~reg0.CLK
clk => counter[1]~reg0.CLK
clk => counter[0]~reg0.CLK
pn <= register[0].DB_MAX_OUTPUT_PORT_TYPE
en => register~6.OUTPUTSELECT
en => register~5.OUTPUTSELECT
en => register~4.OUTPUTSELECT
en => register~3.OUTPUTSELECT
en => register~2.OUTPUTSELECT
en => register~1.OUTPUTSELECT
en => register~0.OUTPUTSELECT
en => counter~7.OUTPUTSELECT
en => counter~6.OUTPUTSELECT
en => counter~5.OUTPUTSELECT
en => counter~4.OUTPUTSELECT
en => counter~3.OUTPUTSELECT
en => counter~2.OUTPUTSELECT
en => counter~1.OUTPUTSELECT
en => counter~0.OUTPUTSELECT
clr => register~13.OUTPUTSELECT
clr => register~12.OUTPUTSELECT
clr => register~11.OUTPUTSELECT
clr => register~10.OUTPUTSELECT
clr => register~9.OUTPUTSELECT
clr => register~8.OUTPUTSELECT
clr => register~7.OUTPUTSELECT
clr => counter[1]~reg0.ENA
clr => counter[0]~reg0.ENA
clr => counter[2]~reg0.ENA
clr => counter[3]~reg0.ENA
clr => counter[4]~reg0.ENA
clr => counter[5]~reg0.ENA
clr => counter[6]~reg0.ENA
clr => counter[7]~reg0.ENA
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[4] <= counter[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[5] <= counter[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[6] <= counter[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[7] <= counter[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE