pn_generator.sim.rpt

用Verilog编写的一个简单的产生伪随机序列的代码（m序列）

; |pn_generator|register~0      ; |pn_generator|register~0      ; out              ;
; |pn_generator|register~1      ; |pn_generator|register~1      ; out              ;
; |pn_generator|register~2      ; |pn_generator|register~2      ; out              ;
; |pn_generator|register~3      ; |pn_generator|register~3      ; out              ;
; |pn_generator|register~4      ; |pn_generator|register~4      ; out              ;
; |pn_generator|register~5      ; |pn_generator|register~5      ; out              ;
; |pn_generator|register~6      ; |pn_generator|register~6      ; out              ;
; |pn_generator|register~7      ; |pn_generator|register~7      ; out              ;
; |pn_generator|register~8      ; |pn_generator|register~8      ; out              ;
; |pn_generator|register~9      ; |pn_generator|register~9      ; out              ;
; |pn_generator|register~10     ; |pn_generator|register~10     ; out              ;
; |pn_generator|register~11     ; |pn_generator|register~11     ; out              ;
; |pn_generator|register~12     ; |pn_generator|register~12     ; out              ;
; |pn_generator|register~13     ; |pn_generator|register~13     ; out              ;
; |pn_generator|counter[0]~reg0 ; |pn_generator|counter[0]~reg0 ; regout           ;
; |pn_generator|counter[2]~reg0 ; |pn_generator|counter[2]~reg0 ; regout           ;
; |pn_generator|counter[3]~reg0 ; |pn_generator|counter[3]~reg0 ; regout           ;
; |pn_generator|counter[4]~reg0 ; |pn_generator|counter[4]~reg0 ; regout           ;
; |pn_generator|counter[5]~reg0 ; |pn_generator|counter[5]~reg0 ; regout           ;
; |pn_generator|counter[6]~reg0 ; |pn_generator|counter[6]~reg0 ; regout           ;
; |pn_generator|counter[7]~reg0 ; |pn_generator|counter[7]~reg0 ; regout           ;
; |pn_generator|register[0]     ; |pn_generator|register[0]     ; regout           ;
; |pn_generator|register[1]     ; |pn_generator|register[1]     ; regout           ;
; |pn_generator|register[2]     ; |pn_generator|register[2]     ; regout           ;
; |pn_generator|register[3]     ; |pn_generator|register[3]     ; regout           ;
; |pn_generator|register[4]     ; |pn_generator|register[4]     ; regout           ;
; |pn_generator|register[5]     ; |pn_generator|register[5]     ; regout           ;
; |pn_generator|register[6]     ; |pn_generator|register[6]     ; regout           ;
; |pn_generator|clk             ; |pn_generator|clk             ; out              ;
; |pn_generator|pn              ; |pn_generator|pn              ; pin_out          ;
; |pn_generator|clr             ; |pn_generator|clr             ; out              ;
; |pn_generator|counter[0]      ; |pn_generator|counter[0]      ; pin_out          ;
; |pn_generator|counter[1]      ; |pn_generator|counter[1]      ; pin_out          ;
; |pn_generator|counter[2]      ; |pn_generator|counter[2]      ; pin_out          ;
; |pn_generator|counter[3]      ; |pn_generator|counter[3]      ; pin_out          ;
; |pn_generator|counter[4]      ; |pn_generator|counter[4]      ; pin_out          ;
; |pn_generator|counter[5]      ; |pn_generator|counter[5]      ; pin_out          ;
; |pn_generator|counter[6]      ; |pn_generator|counter[6]      ; pin_out          ;
; |pn_generator|counter[7]      ; |pn_generator|counter[7]      ; pin_out          ;
; |pn_generator|Add0~40         ; |pn_generator|Add0~40         ; out0             ;
; |pn_generator|Add0~41         ; |pn_generator|Add0~41         ; out0             ;
; |pn_generator|Add0~42         ; |pn_generator|Add0~42         ; out0             ;
; |pn_generator|Add0~43         ; |pn_generator|Add0~43         ; out0             ;
; |pn_generator|Add0~44         ; |pn_generator|Add0~44         ; out0             ;
; |pn_generator|Add0~45         ; |pn_generator|Add0~45         ; out0             ;
; |pn_generator|Add0~46         ; |pn_generator|Add0~46         ; out0             ;
; |pn_generator|Add0~47         ; |pn_generator|Add0~47         ; out0             ;
; |pn_generator|Add0~48         ; |pn_generator|Add0~48         ; out0             ;
; |pn_generator|Add0~49         ; |pn_generator|Add0~49         ; out0             ;
; |pn_generator|Add0~50         ; |pn_generator|Add0~50         ; out0             ;
; |pn_generator|Add0~51         ; |pn_generator|Add0~51         ; out0             ;
; |pn_generator|Add0~52         ; |pn_generator|Add0~52         ; out0             ;
; |pn_generator|Add1~5          ; |pn_generator|Add1~5          ; out0             ;
+-------------------------------+-------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------+
; Missing 1-Value Coverage                                   ;
+--------------------+--------------------+------------------+
; Node Name          ; Output Port Name   ; Output Port Type ;
+--------------------+--------------------+------------------+
; |pn_generator|a[0] ; |pn_generator|a[0] ; out              ;
; |pn_generator|a[1] ; |pn_generator|a[1] ; out              ;
; |pn_generator|a[2] ; |pn_generator|a[2] ; out              ;
; |pn_generator|a[3] ; |pn_generator|a[3] ; out              ;
; |pn_generator|a[4] ; |pn_generator|a[4] ; out              ;
; |pn_generator|a[5] ; |pn_generator|a[5] ; out              ;
; |pn_generator|a[6] ; |pn_generator|a[6] ; out              ;
+--------------------+--------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------+
; Missing 0-Value Coverage                                   ;
+--------------------+--------------------+------------------+
; Node Name          ; Output Port Name   ; Output Port Type ;
+--------------------+--------------------+------------------+
; |pn_generator|a[0] ; |pn_generator|a[0] ; out              ;
; |pn_generator|a[1] ; |pn_generator|a[1] ; out              ;
; |pn_generator|a[2] ; |pn_generator|a[2] ; out              ;
; |pn_generator|a[3] ; |pn_generator|a[3] ; out              ;
; |pn_generator|a[4] ; |pn_generator|a[4] ; out              ;
; |pn_generator|a[5] ; |pn_generator|a[5] ; out              ;
; |pn_generator|a[6] ; |pn_generator|a[6] ; out              ;
; |pn_generator|en   ; |pn_generator|en   ; out              ;
+--------------------+--------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Mon Mar 30 17:28:32 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off pn_generator -c pn_generator
Info: Using vector source file "E:/Design_files/PN_Generator/pn_generator.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Warning: Found clock-sensitive change during active clock edge at time 1.0 ns on register "|pn_generator|register[6]"
Warning: Found clock-sensitive change during active clock edge at time 3.0 ns on register "|pn_generator|counter[0]~reg0"
Warning: Found clock-sensitive change during active clock edge at time 3.0 ns on register "|pn_generator|register[5]"
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      88.57 %
Info: Number of transitions in simulation is 12489
Info: Quartus II Simulator was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 134 megabytes
    Info: Processing ended: Mon Mar 30 17:28:33 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01