pn_generator.v.bak

用Verilog编写的一个简单的产生伪随机序列的代码（m序列）

module pn_generator(a,clk,pn,en,clr,counter);
input [3:0] a;
input clk;
input clr;
input en;
output pn;
output [7:0] counter;
reg[7:0] counter;
reg[3:0] register;
wire pn=register[0];
always @(posedge clk)
begin
if(clr) begin
register <= a;
end
else if (en==1) begin
counter=counter+8'b1;
register [3:0]<={register[0]+register[3],register[3:1]};
end
end
endmodule