pn_generator.map.summary

用Verilog编写的一个简单的产生伪随机序列的代码（m序列）

Analysis & Synthesis Status : Successful - Mon Mar 30 17:20:57 2009
Quartus II Version : 8.1 Build 163 10/28/2008 SJ Full Version
Revision Name : pn_generator
Top-level Entity Name : pn_generator
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 17
    Dedicated logic registers : 15
Total registers : 15
Total pins : 19
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0