📄 labb8.vhd.bak
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library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity greatest is port(pb1,pb2,st,clk:in std_logic; input:in std_logic_vector(7 downto 0); --sum:out std_logic_vector(15 downto 0); number:out std_logic_vector(15 downto 0); done: out std_logic);-- can be sum or largestend greatest;Architecture greatest_arch of greatest issignal state,next_state:integer range 0 to 3;signal v,adder,load_reg1,count_out,comparator_out,load_max_reg:std_logic:='0';signal reg1,max_reg:std_logic_vector(6 downto 0):=(others=>'0');signal sum_out:std_logic_vector(15 downto 0):=(others=>'0');signal count:std_logic_vector(2 downto 0):=(others=>'0');beginprocess(state,v,count_out,comparator_out,st,input) begin load_reg1<='0';adder<='0';load_max_reg<='0';done<='0'; case state is when 0 => if(st='1') then next_state<=1; else next_state<=0; end if; when 1 => if(v='1') then load_reg1<='1'; adder<='1'; next_state<=2; else load_reg1<='0'; adder<='0'; next_state<=1; end if;when 2=> if(count_out='1')then next_state<=3; else if(comparator_out='1')then load_max_reg<='1'; else load_max_reg<='0'; end if; next_state<=1; end if;when 3=>if(st='1')then next_state<=3; else next_state<=0; done<='1'; end if;end case;end process;process(clk)beginif(clk'event and clk='1')then state<=next_state; if(load_reg1='1')then reg1<=input(6 downto 0); count<=count+1;end if; if(load_max_reg ='1')then max_reg<=reg1;end if; end if; end process; count_out<='1' when count="111" else '0'; v<='1' when input(7)='1'else '0'; comparator_out<='1' when (reg1>max_reg)else '0'; sum_out<=sum_out+reg1 when (adder='1') else sum_out; number<=sum_out when(pb1='1') else "000000000"& max_reg when (pb2='1') else (others=>'0'); end greatest_arch;
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