lab8.vhd.bak

this is vhdl program for two address method

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity largest is
   port(pb1,pb2,pb,st,clk:in std_logic;
        input:in std_logic_vector(7 downto 0);
        --sum:out std_logic_vector(15 downto 0);
       number:out std_logic_vector(15 downto 0);
       done: out std_logic);-- can be sum or largest
end largest;

Architecture largest_arch of largest is
type ROM is array (0 to 6)of std_logic_vector(19 downto 0);
constant ROMVALUE:ROM:=("00000000110000000000","00110101011000001000","01001111011100000000","01110110011110000100","10010000111111000010",
                          "10110100111111100000","11100011011111110001");
signal state,next_state,next_state_true,next_state_false:std_logic_vector(2 downto 0);
signal v,sel,adder,load_reg,count_out,comparator_out,load_max_reg,led_0,led_1,led_2,led_3,led_4,led_5,led_6:std_logic:='0';
signal reg,max_reg:std_logic_vector(6 downto 0):=(others=>'0');
signal sum_out:std_logic_vector(15 downto 0):=(others=>'0');
signal count:std_logic_vector(3 downto 0):=(others=>'0');
signal condition :std_logic_vector(2 downto 0):=(others=>'0');
signal Rom_out:std_logic_vector(19 downto 0):=(others=>'0');
signal temp:std_logic_vector(8 downto 0):=(others=>'0');
begin
  Rom_out<=ROMVALUE(conv_integer(state));
  condition<=Rom_out(19 downto 17);
  next_state_false<=Rom_out( 16 downto 14);
  next_state_true<= Rom_out(13 downto 11);
  led_0<=Rom_out(10);
  led_1<=Rom_out(9);
  led_2<=Rom_out(8);
  led_3<=Rom_out(7);
  led_4<=Rom_out(6);
  led_5<=Rom_out(5);
  led_6<=Rom_out(4);
  load_reg<=Rom_out(3);
  adder<=Rom_out(2);
  load_max_reg<=Rom_out(1);
  Done<=Rom_out(0);

sel<=st when (condition="000") else
      v when (condition="001" ) else
      count_out when (condition="010") else
      comparator_out when (condition="011")else
      pb              when (condition="100") else
      pb               when(condition="101")else
      st;
      
      
      
      
      
next_state<= next_state_true when (sel='1') else
             next_state_false when  (sel='0');
             
count_out<='1' when count="0100" else '0';
 v<='1' when input(7)='1'else '0';
 comparator_out<='1' when (reg>max_reg) else '0';
 --sum_out<=sum_out + (temp&reg) when (adder='1') else sum_out;
 number<=sum_out when(pb1='1') else 
          "000000000"& max_reg when (pb2='1') else (others=>'0');
    --present_state<=ROM
          
      
process(clk)
begin
if(clk'event and clk='1')then
    state<=next_state;
    if(adder='1')then
      sum_out<=sum_out + (temp&reg); end if;
    if(load_reg='1')then
      reg<=input(6 downto 0);
      count<=count+1;end if;
      if(count="0100") then
        count<="0000";end if;
  if(load_max_reg ='1')then
    max_reg<=reg;end if;
  end if;
 end process;
 
  end largest_arch;