os_cpu_a.s

《嵌入式网络系统设计-基于Atmel ARM7 系列》这个本书的光盘资料

;********************************************************************************************************
;                                               uC/OS-II
;                                         The Real-Time Kernel
;
;                               (c) Copyright 1992-2004, Micrium, Weston, FL
;                                          All Rights Reserved
;
;                                               ARM7 Port
;                                            IAR C Compiler
;
; File : OS_CPU_A.ASM
; By   : Jean J. Labrosse
;********************************************************************************************************
		AREA  |subr|, CODE, READONLY
		
		INCLUDE 	/at91sam7x256/include/arm7tdmi/arm.inc
		INCLUDE		/at91sam7x256/include/AT91SAM7X256.inc


   


        
        EXPORT 	ARMDisableInt
		EXPORT 	ARMEnableInt
        
        EXPORT  OS_CPU_SR_Save
        EXPORT  OS_CPU_SR_Restore


NO_INT  EQU     0xC0                             ; Mask used to disable interrupts (Both FIR and IRQ)
;*********************************************************************************************************
;                                   CRITICAL SECTION METHOD 3 FUNCTIONS
;
; Description: Disable/Enable interrupts by preserving the state of interrupts.  Generally speaking you
;              would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
;              disable interrupts.  'cpu_sr' is allocated in all of uC/OS-II's functions that need to 
;              disable interrupts.  You would restore the interrupt disable state by copying back 'cpu_sr'
;              into the CPU's status register.
;
; Prototypes :     OS_CPU_SR  OS_CPU_SR_Save(void);
;                  void       OS_CPU_SR_Restore(OS_CPU_SR cpu_sr);
;
;
; Note(s)    : 1) These functions are used in general like this:
;
;                 void Task (void *p_arg)
;                 {
;                 #if OS_CRITICAL_METHOD == 3          /* Allocate storage for CPU status register */
;                     OS_CPU_SR  cpu_sr;
;                 #endif
;
;                          :
;                          :
;                     OS_ENTER_CRITICAL();             /* cpu_sr = OS_CPU_SaveSR();                */
;                          :
;                          :
;                     OS_EXIT_CRITICAL();              /* OS_CPU_RestoreSR(cpu_sr);                */
;                          :
;                          :
;                 }
;
;              2) OS_CPU_SaveSR() is implemented as recommended by Atmels application note:
;
;                    "Disabling Interrupts at Processor Level"
;*********************************************************************************************************
OS_CPU_SR_Save
        MRS     R0,CPSR                     ; Set IRQ and FIQ bits in CPSR to disable all interrupts
        ORR     R1,R0,#NO_INT
        MSR     CPSR_c,R1
        MRS     R1,CPSR                     ; Confirm that CPSR contains the proper interrupt disable flags
        AND     R1,R1,#NO_INT
        CMP     R1,#NO_INT
        BNE     OS_CPU_SR_Save              ; Not properly disabled (try again)
        MOV     PC,LR                       ; Disabled, return the original CPSR contents in R0


OS_CPU_SR_Restore
        MSR     CPSR_c,R0
        MOV     PC,LR
        
ARMDisableInt             	    
		MRS     R12, CPSR           		; get current CPU mode
  		ORR     R12, R12, #I_BIT    		; set the interrupt disable mode bit
  		MSR     CPSR_c, R12         
  		BX		LR                  


ARMEnableInt
  		MRS 	R12, CPSR             		; move current processor status into reg 12  
  		BIC 	R12, R12, #I_BIT      		; clear the interrupt disable bit
  		MSR 	CPSR_c, R12           
  		BX		LR         

        
        END