最终.txt

自己写的东西,可以参考,请注意下载,别乱来,

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity sfifo is
	generic
	(
		width:positive:= 16;
		depth:positive:= 16
	);
	port
	(
		clk:in std_logic;
		rst:in std_logic;
		wq:in std_logic;
		rq:in std_logic;
		data:in std_logic_vector(width - 1 downto 0);
		q:out std_logic_vector(width - 1 downto 0);
		empty:out td_logic;
		full:out std_logic
	);
end entity sfifo;
architecture structure of sfifo is
signal	empty_t:std_logic;
signal	full_t:std_logic;
signal	wr_pt:std_logic_vector(depth - 1 downto 0);
signal	rd_pt:std_logic_vector(depth - 1 downto 0);
signal	wr:std_logic;
signal	rd:std_logic;
component write_pointer
	generic
	(
		depth:positive:=16	
	);
	port
	(
		clk:in std_logic;
		rst:in std_logic;
		wq:in std_logic;
		full:in std_logic;
		wr:out std_logic;
		wr_pt:out std_logic_vector(depth - 1 downto 0)
	);
end component;
component read_pointer
	generic
	(
		depth:positive:=16	
	);
	port
	(
		clk:in std_logic;
		rst:in std_logic;
		rq:in std_logic;
		empty:in std_logic;
		rd:out std_logic;
		rd_pt:out std_logic_vector(depth - 1 downto 0)
	);
end component;

component judge_status
	generic
	(
		depth:positive :=16
	);
	port
	(
		clk:in std_logic;
		rst:in std_logic;
		wr_pt:in std_logic_vector(depth - 1 downto 0);
		rd_pt:in std_logic_vector(depth - 1 downto 0);
		empty:out std_logic;
		full:out std_logic
	);
end component;
component dualram
	generic
	(
		width:positive:= 16;
		depth:positive:= 16
	);
	port
	(
		clka:in std_logic;
		wr:in std_logic;
		addra:in std_logic_vector(depth - 1 downto 0);
		datain:in std_logic_vector(width - 1 downto 0);
		clkb:in std_logic;
		rd:in std_logic;
		addrb:in std_logic_vector(depth - 1 downto 0);
		dataout:out std_logic_vector(width - 1 downto 0)
	);
end component;
begin 
	empty<=empty_t;
	full<=full_t;
	u0:dualram
	generic map
	(
		width=>width;
		depth=>depth
	)
	port map
	(
        clka=>clk;
        wr=>wr;
        addra=>wr_pt;
        datain=>data;
        clkb=>clk;
        rd=>rd;
        addrb=>rd_pt;
        dataout=>q
	);
	u1:write_pointer
	generic map
	(
		depth=>depth
	)
	port map
	(
	    clk=>clk;
	    rst=>rst;
	    wq=>wq;
	    full=>full_t;
	    wr=>wr;
	    wr_pt=>wr_pt	
	);
	
	u2:read_pointer
	generic map
	(
		depth=>depth
	)
	port map
	(
	    clk=>clk;	
	    rst=>rst;
	    rq=>rq;
	    empty=>empty_t;
	    rd=>rd;
	    rd_pt=>rd_pt
	);
	
	u3:judge_status
	generic map
	(
		depth=>depth
	)
	port map
	(
		clk=> clk;
	    rst=>rst;
	    wr_pt=>wr_pt;
	    rd_pt=>rd_pt;
	    empty=>empty_t;
	    full=>full_t	
	);
	end structure;