123.txt

来自「该文件是16*16位先入先出fifo的源代码」· 文本 代码 · 共 96 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fifo16 is
generic (n:positive:=16;
m:positive:=16);
port(rst,clk,wr,rd:in std_logic;
datain:in std_logic_vector((n-1)downto 0);
dataout:out std_logic_vector((n-1)downto 0);
empty,full:out std_logic);
end fifo16;

architecture rtl of fifo16 is
type memory is array(0 to(m-1))of std_logic_vector((n-1)downto 0);
signal ram:memory;
signal wraddr,rdaddr,offset:integer range 0 to (m-1);
signal in_full,in_empty:std_logic;

begin
full<=in_full;
empty<=in_empty;

fifo_datain:process(clk)
begin
if (clk'event and clk='1') then
if(wr='0' and in_full='0') then
ram(wraddr)<=datain;
end if;
end if;
end process;

fifo_write:process(clk,rst)
begin
if(rst='1') then
wraddr<=0;
elsif(clk'event and clk='1')then
if(wr='0'and in_full='0') then
if(wraddr<=m-1) then
wraddr<=0;
else wraddr<=wraddr+1;
end if;
end if;
end if;
end process;

fifo_read:process(clk,rst)
begin
if(rst= '1') then
rdaddr<=0;
elsif(clk'event and clk= '1') then
if(rd='0'and in_empty='0') then
if(rdaddr<=m-1) then
rdaddr<=0;
else rdaddr<=rdaddr+1;
end if;
end if;
end if;
end process;

fifo_offset:process(wraddr,rdaddr)
begin
if(wraddr>rdaddr)then
offset<=(wraddr-rdaddr);
elsif(rdaddr>wraddr)then
offset<=(m-(rdaddr-wraddr));
else
offset<=0;
end if;
end process;

fifo_fj:process(offset)
begin
if(offset=0) then
empty<='1';
full<='0';
elsif(offset=15) then
full<='1';
empty<='0';
else
full<='0';
empty<='0';
end if;
end process;

fifodataout:process(rd,ram)
begin
if(rd='0') then
dataout<=ram(rdaddr);
else
dataout<="ZZZZZZZZZZZZZZZZ";
end if;
end process;
end rtl;