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📄 stm32f10x_tim.txt

📁 ucos2.86版本结合STM板极支持包
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;;;1090   
                          ENDP

                  TIM_OC3PreloadConfig PROC
;;;1109   
;;;1110     tmpccmr2 = TIMx->CCMR2;
000514  8b82              LDRH     r2,[r0,#0x1c]
;;;1111   
;;;1112     /* Reset the OCPE Bit */
;;;1113     tmpccmr2 &= CCMR_OC13PE_Mask;
000516  f647f647          MOV      r3,#0x7f77
00051a  401a              ANDS     r2,r2,r3
;;;1114   
;;;1115     /* Enable or Disable the Output Compare Preload feature */
;;;1116     tmpccmr2 |= TIM_OCPreload;
00051c  4311              ORRS     r1,r1,r2
;;;1117   
;;;1118     TIMx->CCMR2 = (u16)tmpccmr2;
00051e  8381              STRH     r1,[r0,#0x1c]
;;;1119   }
000520  4770              BX       lr
;;;1120   
                          ENDP

                  TIM_OC4PreloadConfig PROC
;;;1139   
;;;1140     tmpccmr2 = TIMx->CCMR2;
000522  8b82              LDRH     r2,[r0,#0x1c]
;;;1141   
;;;1142     /* Reset the OCPE Bit */
;;;1143     tmpccmr2 &= CCMR_OC24PE_Mask;
000524  f247f247          MOV      r3,#0x777f
000528  401a              ANDS     r2,r2,r3
;;;1144   
;;;1145     /* Enable or Disable the Output Compare Preload feature */
;;;1146     tmpccmr2 |= (u16)(TIM_OCPreload << 8);
00052a  ea42ea42          ORR      r1,r2,r1,LSL #8
;;;1147   
;;;1148     TIMx->CCMR2 = (u16)tmpccmr2;
00052e  8381              STRH     r1,[r0,#0x1c]
;;;1149   }
000530  4770              BX       lr
;;;1150   
                          ENDP

                  TIM_OC1FastConfig PROC
;;;1168   
;;;1169     tmpccmr1 = TIMx->CCMR1;
000532  8b02              LDRH     r2,[r0,#0x18]
;;;1170   
;;;1171     /* Reset the OCFE Bit */
;;;1172     tmpccmr1 &= CCMR_OC13FE_Mask;
000534  f647f647          MOV      r3,#0x7f7b
000538  401a              ANDS     r2,r2,r3
;;;1173   
;;;1174     /* Enable or Disable the Output Compare Fast Bit */
;;;1175     tmpccmr1 |= TIM_OCFast;
00053a  4311              ORRS     r1,r1,r2
;;;1176   
;;;1177     TIMx->CCMR1 = (u16)tmpccmr1;
00053c  8301              STRH     r1,[r0,#0x18]
;;;1178   }
00053e  4770              BX       lr
;;;1179   
                          ENDP

                  TIM_OC2FastConfig PROC
;;;1197   
;;;1198     tmpccmr1 = TIMx->CCMR1;
000540  8b02              LDRH     r2,[r0,#0x18]
;;;1199   
;;;1200     /* Reset the OCFE Bit */
;;;1201     tmpccmr1 &= CCMR_OC24FE_Mask;
000542  f647f647          MOV      r3,#0x7b7f
000546  401a              ANDS     r2,r2,r3
;;;1202   
;;;1203     /* Enable or Disable the Output Compare Fast Bit */
;;;1204     tmpccmr1 |= (u16)(TIM_OCFast << 8);
000548  ea42ea42          ORR      r1,r2,r1,LSL #8
;;;1205   
;;;1206     TIMx->CCMR1 = (u16)tmpccmr1;
00054c  8301              STRH     r1,[r0,#0x18]
;;;1207   }
00054e  4770              BX       lr
;;;1208   
                          ENDP

                  TIM_OC3FastConfig PROC
;;;1226   
;;;1227     tmpccmr2 = TIMx->CCMR2;
000550  8b82              LDRH     r2,[r0,#0x1c]
;;;1228   
;;;1229     /* Reset the OCFE Bit */
;;;1230     tmpccmr2 &= CCMR_OC13FE_Mask;
000552  f647f647          MOV      r3,#0x7f7b
000556  401a              ANDS     r2,r2,r3
;;;1231   
;;;1232     /* Enable or Disable the Output Compare Fast Bit */
;;;1233     tmpccmr2 |= TIM_OCFast;
000558  4311              ORRS     r1,r1,r2
;;;1234   
;;;1235     TIMx->CCMR2 = (u16)tmpccmr2;
00055a  8381              STRH     r1,[r0,#0x1c]
;;;1236   }
00055c  4770              BX       lr
;;;1237   
                          ENDP

                  TIM_OC4FastConfig PROC
;;;1255   
;;;1256     tmpccmr2 = TIMx->CCMR2;
00055e  8b82              LDRH     r2,[r0,#0x1c]
;;;1257   
;;;1258     /* Reset the OCFE Bit */
;;;1259     tmpccmr2 &= CCMR_OC24FE_Mask;
000560  f647f647          MOV      r3,#0x7b7f
000564  401a              ANDS     r2,r2,r3
;;;1260   
;;;1261     /* Enable or Disable the Output Compare Fast Bit */
;;;1262     tmpccmr2 |= (u16)(TIM_OCFast << 8);
000566  ea42ea42          ORR      r1,r2,r1,LSL #8
;;;1263   
;;;1264     TIMx->CCMR2 = (u16)tmpccmr2;
00056a  8381              STRH     r1,[r0,#0x1c]
;;;1265   }
00056c  4770              BX       lr
;;;1266   
                          ENDP

                  TIM_ClearOC1Ref PROC
;;;1284   
;;;1285     tmpccmr1 = TIMx->CCMR1;
00056e  8b02              LDRH     r2,[r0,#0x18]
;;;1286   
;;;1287     /* Reset the OCFE Bit */
;;;1288     tmpccmr1 &= CCMR_OC13CE_Mask;
000570  f64ff64f          MOV      r3,#0xff7f
000574  401a              ANDS     r2,r2,r3
;;;1289   
;;;1290     /* Enable or Disable the Output Compare Clear Bit */
;;;1291     tmpccmr1 |= (u16)(TIM_OCClear);
000576  4311              ORRS     r1,r1,r2
;;;1292   
;;;1293     TIMx->CCMR1 = (u16)tmpccmr1;
000578  8301              STRH     r1,[r0,#0x18]
;;;1294   }
00057a  4770              BX       lr
;;;1295   
                          ENDP

                  TIM_ClearOC2Ref PROC
;;;1313   
;;;1314     tmpccmr1 = TIMx->CCMR1;
00057c  8b02              LDRH     r2,[r0,#0x18]
;;;1315   
;;;1316     /* Reset the OCFE Bit */
;;;1317     tmpccmr1 &= CCMR_OC24CE_Mask;
00057e  f3c2f3c2          UBFX     r2,r2,#0,#15
;;;1318   
;;;1319     /* Enable or Disable the Output Compare Clear Bit */
;;;1320     tmpccmr1 |= (u16)(TIM_OCClear << 8);
000582  ea42ea42          ORR      r1,r2,r1,LSL #8
;;;1321   
;;;1322     TIMx->CCMR1 = (u16)tmpccmr1;
000586  8301              STRH     r1,[r0,#0x18]
;;;1323   }
000588  4770              BX       lr
;;;1324   
                          ENDP

                  TIM_ClearOC3Ref PROC
;;;1342   
;;;1343     tmpccmr2 = TIMx->CCMR2;
00058a  8b82              LDRH     r2,[r0,#0x1c]
;;;1344   
;;;1345     /* Reset the OCFE Bit */
;;;1346     tmpccmr2 &= CCMR_OC13CE_Mask;
00058c  f64ff64f          MOV      r3,#0xff7f
000590  401a              ANDS     r2,r2,r3
;;;1347   
;;;1348     /* Enable or Disable the Output Compare Clear Bit */
;;;1349     tmpccmr2 |= (u16)(TIM_OCClear);
000592  4311              ORRS     r1,r1,r2
;;;1350   
;;;1351     TIMx->CCMR2 = (u16)tmpccmr2;
000594  8381              STRH     r1,[r0,#0x1c]
;;;1352   }
000596  4770              BX       lr
;;;1353   
                          ENDP

                  TIM_ClearOC4Ref PROC
;;;1371   
;;;1372     tmpccmr2 = TIMx->CCMR2;
000598  8b82              LDRH     r2,[r0,#0x1c]
;;;1373   
;;;1374     /* Reset the OCFE Bit */
;;;1375     tmpccmr2 &= CCMR_OC24CE_Mask;
00059a  f3c2f3c2          UBFX     r2,r2,#0,#15
;;;1376   
;;;1377     /* Enable or Disable the Output Compare Clear Bit */
;;;1378     tmpccmr2 |= (u16)(TIM_OCClear << 8);
00059e  ea42ea42          ORR      r1,r2,r1,LSL #8
;;;1379   
;;;1380     TIMx->CCMR2 = (u16)tmpccmr2;
0005a2  8381              STRH     r1,[r0,#0x1c]
;;;1381   }
0005a4  4770              BX       lr
;;;1382   
                          ENDP

                  TIM_UpdateDisableConfig PROC
;;;1398   
;;;1399     tmpcr1 = TIMx->CR1;
0005a6  8802              LDRH     r2,[r0,#0]
;;;1400   
;;;1401     if (Newstate != DISABLE)
0005a8  b111              CBZ      r1,|L1.1456|
;;;1402     {
;;;1403       /* Set the Update Disable Bit */
;;;1404       tmpcr1 |= CR1_UDIS_Set;
0005aa  f042f042          ORR      r1,r2,#2
0005ae  e002              B        |L1.1462|
                  |L1.1456|
;;;1405     }
;;;1406     else
;;;1407     {
;;;1408       /* Reset the Update Disable Bit */
;;;1409       tmpcr1 &= CR1_UDIS_Reset;
0005b0  f240f240          MOV      r1,#0x3fd
0005b4  4011              ANDS     r1,r1,r2
                  |L1.1462|
;;;1410     }
;;;1411   
;;;1412     TIMx->CR1 = (u16)tmpcr1;
0005b6  8001              STRH     r1,[r0,#0]
;;;1413   }
0005b8  4770              BX       lr
;;;1414   
                          ENDP

                  TIM_EncoderInterfaceConfig PROC
;;;1439                                   u16 TIM_IC1Polarity, u16 TIM_IC2Polarity)
;;;1440   {
0005ba  b470              PUSH     {r4-r6}
;;;1441     u32 tmpsmcr = 0;
;;;1442     u32 tmpccmr1 = 0;
;;;1443     u32 tmpccer = 0;
;;;1444       
;;;1445     /* Check the parameters */
;;;1446     assert(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
;;;1447     assert(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
;;;1448     assert(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
;;;1449   
;;;1450     tmpsmcr = TIMx->SMCR;
0005bc  8905              LDRH     r5,[r0,#8]
;;;1451     tmpccmr1 = TIMx->CCMR1;
0005be  8b04              LDRH     r4,[r0,#0x18]
;;;1452     tmpccer = TIMx->CCER;
0005c0  f8b0f8b0          LDRH     r12,[r0,#0x20]
;;;1453   
;;;1454     /* Set the encoder Mode */
;;;1455     tmpsmcr &= SMCR_SMS_Mask;
0005c4  f64ff64f          MOV      r6,#0xfff0
0005c8  4035              ANDS     r5,r5,r6
;;;1456     tmpsmcr |= TIM_EncoderMode;
0005ca  4329              ORRS     r1,r1,r5
;;;1457   
;;;1458     /* Select the Capture Compare 1 and the Capture Compare 2 as input */
;;;1459     tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
0005cc  f647f647          MOV      r5,#0x7c7c
0005d0  402c              ANDS     r4,r4,r5
;;;1460     tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
0005d2  f240f240          MOV      r5,#0x101
0005d6  432c              ORRS     r4,r4,r5
;;;1461   
;;;1462     /* Set the TI1 and the TI2 Polarities */
;;;1463     tmpccer &= CCER_CC1P_Mask & CCER_CC2P_Mask;
0005d8  f64ff64f          MOV      r5,#0xffdd
0005dc  ea0cea0c          AND      r12,r12,r5
;;;1464     tmpccer |= (TIM_IC1Polarity | (u16)((u16)TIM_IC2Polarity << 4));
0005e0  ea42ea42          ORR      r2,r2,r3,LSL #4
0005e4  ea42ea42          ORR      r2,r2,r12
;;;1465   
;;;1466     TIMx->SMCR = (u16)tmpsmcr;
0005e8  8101              STRH     r1,[r0,#8]
;;;1467   
;;;1468     TIMx->CCMR1 = (u16)tmpccmr1;
0005ea  8304              STRH     r4,[r0,#0x18]
;;;1469   
;;;1470     TIMx->CCER = (u16)tmpccer;
0005ec  8402              STRH     r2,[r0,#0x20]
;;;1471   }
0005ee  bc70              POP      {r4-r6}
0005f0  4770              BX       lr
;;;1472   
                          ENDP

                  TIM_GenerateEvent PROC
;;;1493     /* Set the event sources */
;;;1494     TIMx->EGR |= TIM_EventSource;
0005f2  8a82              LDRH     r2,[r0,#0x14]
0005f4  4311              ORRS     r1,r1,r2
0005f6  8281              STRH     r1,[r0,#0x14]
;;;1495   }
0005f8  4770              BX       lr
;;;1496   
                          ENDP

                  TIM_OC1PolarityConfig PROC
;;;1514   
;;;1515     tmpccer = TIMx->CCER;
0005fa  8c02              LDRH     r2,[r0,#0x20]
;;;1516   
;;;1517     /* Set or Reset the CC1P Bit */
;;;1518     tmpccer &= CCER_CC1P_Mask;
0005fc  f64ff64f          MOV      r3,#0xfffd
000600  401a              ANDS     r2,r2,r3
;;;1519     tmpccer |= TIM_OCPolarity;
000602  4311              ORRS     r1,r1,r2
;;;1520   
;;;1521     TIMx->CCER = (u16)tmpccer;
000604  8401              STRH     r1,[r0,#0x20]
;;;1522   }
000606  4770              BX       lr
;;;1523   
                          ENDP

                  TIM_OC2PolarityConfig PROC
;;;1541   
;;;1542     tmpccer = TIMx->CCER;
000608  8c02              LDRH     r2,[r0,#0x20]
;;;1543   
;;;1544     /* Set or Reset the CC2P Bit */
;;;1545     tmpccer &= CCER_CC2P_Mask;
00060a  f64ff64f          MOV      r3,#0xffdf
00060e  401a              ANDS     r2,r2,r3
;;;1546     tmpccer |= (u16)((u16)TIM_OCPolarity << 4);

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