📄 stm32f10x_tim.txt
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0003f2 2201 MOVS r2,#1
0003f4 4620 MOV r0,r4
0003f6 f7fff7ff BL TI1_Config
|L1.1018|
;;;632 }
;;;633
;;;634 /* Select the Trigger source */
;;;635 TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
0003fa 4629 MOV r1,r5
0003fc 4620 MOV r0,r4
0003fe f7fff7ff BL TIM_SelectInputTrigger
;;;636
;;;637 /* Select the External clock mode1 */
;;;638 TIMx->SMCR |= TIM_SlaveMode_External1;
000402 8920 LDRH r0,[r4,#8]
000404 f040f040 ORR r0,r0,#7
000408 8120 STRH r0,[r4,#8]
;;;639 }
00040a bd30 POP {r4,r5,pc}
;;;640
ENDP
TIM_ETRConfig PROC
;;;735
;;;736 tmpsmcr = TIMx->SMCR;
00040c f8b0f8b0 LDRH r12,[r0,#8]
;;;737
;;;738 /* Set the Prescaler, the Filter value and the Polarity */
;;;739 tmpsmcr &= SMCR_ETR_Mask;
000410 f00cf00c AND r12,r12,#0xf7
;;;740 tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (u16)((u16)ExtTRGFilter << 8);
000414 4311 ORRS r1,r1,r2
000416 ea41ea41 ORR r1,r1,r3,LSL #8
00041a ea41ea41 ORR r1,r1,r12
;;;741
;;;742 TIMx->SMCR = (u16)tmpsmcr;
00041e 8101 STRH r1,[r0,#8]
;;;743 }
000420 4770 BX lr
;;;744
ENDP
TIM_ETRClockMode1Config PROC
;;;661 u8 ExtTRGFilter)
;;;662 {
000422 b510 PUSH {r4,lr}
000424 4604 MOV r4,r0
;;;663 /* Check the parameters */
;;;664 assert(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;665 assert(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;666
;;;667 /* Configure the ETR Clock source */
;;;668 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
000426 4620 MOV r0,r4
000428 f7fff7ff BL TIM_ETRConfig
;;;669
;;;670 /* Select the External clock mode1 */
;;;671 TIMx->SMCR &= SMCR_SMS_Mask;
00042c 8920 LDRH r0,[r4,#8]
00042e f020f020 BIC r0,r0,#0xf
000432 8120 STRH r0,[r4,#8]
;;;672 TIMx->SMCR |= TIM_SlaveMode_External1;
000434 8920 LDRH r0,[r4,#8]
000436 f040f040 ORR r0,r0,#7
00043a 8120 STRH r0,[r4,#8]
;;;673
;;;674 /* Select the Trigger selection : ETRF */
;;;675 TIMx->SMCR &= SMCR_TS_Mask;
00043c 8920 LDRH r0,[r4,#8]
00043e f020f020 BIC r0,r0,#0x78
000442 8120 STRH r0,[r4,#8]
;;;676 TIMx->SMCR |= TIM_TS_ETRF;
000444 8920 LDRH r0,[r4,#8]
000446 f040f040 ORR r0,r0,#0x70
00044a 8120 STRH r0,[r4,#8]
;;;677 }
00044c bd10 POP {r4,pc}
;;;678
ENDP
TIM_ETRClockMode2Config PROC
;;;699 u16 TIM_ExtTRGPolarity, u8 ExtTRGFilter)
;;;700 {
00044e b510 PUSH {r4,lr}
000450 4604 MOV r4,r0
;;;701 /* Check the parameters */
;;;702 assert(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;703 assert(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;704
;;;705 /* Configure the ETR Clock source */
;;;706 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
000452 4620 MOV r0,r4
000454 f7fff7ff BL TIM_ETRConfig
;;;707
;;;708 /* Enable the External clock mode2 */
;;;709 TIMx->SMCR |= SMCR_ECE_Set;
000458 8920 LDRH r0,[r4,#8]
00045a f440f440 ORR r0,r0,#0x4000
00045e 8120 STRH r0,[r4,#8]
;;;710 }
000460 bd10 POP {r4,pc}
000462 0000 DCW 0x0000
|L1.1124|
000464 00000000 DCD Tab_OCModeMask
|L1.1128|
000468 00000000 DCD Tab_PolarityMask
ENDP
TIM_PrescalerConfig PROC
;;;797 /* Set the Prescaler value */
;;;798 TIMx->PSC = Prescaler;
00046c 8501 STRH r1,[r0,#0x28]
;;;799
;;;800 /* Set or reset the UG Bit */
;;;801 if (TIM_PSCReloadMode == TIM_PSCReloadMode_Immediate)
00046e 2a01 CMP r2,#1
000470 d104 BNE |L1.1148|
;;;802 {
;;;803 TIMx->EGR |= TIM_EventSource_Update;
000472 8a81 LDRH r1,[r0,#0x14]
000474 f041f041 ORR r1,r1,#1
000478 8281 STRH r1,[r0,#0x14]
;;;804 }
;;;805 else
;;;806 {
;;;807 TIMx->EGR &= TIM_EventSource_Update;
;;;808 }
;;;809 }
00047a 4770 BX lr
|L1.1148|
00047c 8a81 LDRH r1,[r0,#0x14]
00047e f001f001 AND r1,r1,#1
000482 8281 STRH r1,[r0,#0x14]
000484 4770 BX lr
;;;810
ENDP
TIM_CounterModeConfig PROC
;;;831
;;;832 tmpcr1 = TIMx->CR1;
000486 8802 LDRH r2,[r0,#0]
;;;833
;;;834 /* Reset the CMS and DIR Bits */
;;;835 tmpcr1 &= CR1_CounterMode_Mask;
000488 f240f240 MOV r3,#0x39f
00048c 401a ANDS r2,r2,r3
;;;836
;;;837 /* Set the Counter Mode */
;;;838 tmpcr1 |= TIM_CounterMode;
00048e 4311 ORRS r1,r1,r2
;;;839
;;;840 TIMx->CR1 = (u16)tmpcr1;
000490 8001 STRH r1,[r0,#0]
;;;841 }
000492 4770 BX lr
;;;842
ENDP
TIM_ForcedOC1Config PROC
;;;862
;;;863 tmpccmr1 = TIMx->CCMR1;
000494 8b02 LDRH r2,[r0,#0x18]
;;;864
;;;865 /* Reset the OCM Bits */
;;;866 tmpccmr1 &= CCMR_OCM13_Mask;
000496 f647f647 MOV r3,#0x7f0f
00049a 401a ANDS r2,r2,r3
;;;867
;;;868 /* Configure The Forced output Mode */
;;;869 tmpccmr1 |= TIM_ForcedAction;
00049c 4311 ORRS r1,r1,r2
;;;870
;;;871 TIMx->CCMR1 = (u16)tmpccmr1;
00049e 8301 STRH r1,[r0,#0x18]
;;;872 }
0004a0 4770 BX lr
;;;873
ENDP
TIM_ForcedOC2Config PROC
;;;893
;;;894 tmpccmr1 = TIMx->CCMR1;
0004a2 8b02 LDRH r2,[r0,#0x18]
;;;895
;;;896 /* Reset the OCM Bits */
;;;897 tmpccmr1 &= CCMR_OCM24_Mask;
0004a4 f640f640 MOV r3,#0xf7f
0004a8 401a ANDS r2,r2,r3
;;;898
;;;899 /* Configure The Forced output Mode */
;;;900 tmpccmr1 |= (u16)(TIM_ForcedAction << 8);
0004aa ea42ea42 ORR r1,r2,r1,LSL #8
;;;901
;;;902 TIMx->CCMR1 = (u16)tmpccmr1;
0004ae 8301 STRH r1,[r0,#0x18]
;;;903 }
0004b0 4770 BX lr
;;;904
ENDP
TIM_ForcedOC3Config PROC
;;;924
;;;925 tmpccmr2 = TIMx->CCMR2;
0004b2 8b82 LDRH r2,[r0,#0x1c]
;;;926
;;;927 /* Reset the OCM Bits */
;;;928 tmpccmr2 &= CCMR_OCM13_Mask;
0004b4 f647f647 MOV r3,#0x7f0f
0004b8 401a ANDS r2,r2,r3
;;;929
;;;930 /* Configure The Forced output Mode */
;;;931 tmpccmr2 |= TIM_ForcedAction;
0004ba 4311 ORRS r1,r1,r2
;;;932
;;;933 TIMx->CCMR2 = (u16)tmpccmr2;
0004bc 8381 STRH r1,[r0,#0x1c]
;;;934 }
0004be 4770 BX lr
;;;935
ENDP
TIM_ForcedOC4Config PROC
;;;955
;;;956 tmpccmr2 = TIMx->CCMR2;
0004c0 8b82 LDRH r2,[r0,#0x1c]
;;;957
;;;958 /* Reset the OCM Bits */
;;;959 tmpccmr2 &= CCMR_OCM24_Mask;
0004c2 f640f640 MOV r3,#0xf7f
0004c6 401a ANDS r2,r2,r3
;;;960
;;;961 /* Configure The Forced output Mode */
;;;962 tmpccmr2 |= (u16)(TIM_ForcedAction << 8);
0004c8 ea42ea42 ORR r1,r2,r1,LSL #8
;;;963
;;;964 TIMx->CCMR2 = (u16)tmpccmr2;
0004cc 8381 STRH r1,[r0,#0x1c]
;;;965 }
0004ce 4770 BX lr
;;;966
ENDP
TIM_ARRPreloadConfig PROC
;;;982
;;;983 tmpcr1 = TIMx->CR1;
0004d0 8802 LDRH r2,[r0,#0]
;;;984
;;;985 if (Newstate != DISABLE)
0004d2 b111 CBZ r1,|L1.1242|
;;;986 {
;;;987 /* Set the ARR Preload Bit */
;;;988 tmpcr1 |= CR1_ARPE_Set;
0004d4 f042f042 ORR r1,r2,#0x80
0004d8 e002 B |L1.1248|
|L1.1242|
;;;989 }
;;;990 else
;;;991 {
;;;992 /* Reset the ARR Preload Bit */
;;;993 tmpcr1 &= CR1_ARPE_Reset;
0004da f240f240 MOV r1,#0x37f
0004de 4011 ANDS r1,r1,r2
|L1.1248|
;;;994 }
;;;995
;;;996 TIMx->CR1 = (u16)tmpcr1;
0004e0 8001 STRH r1,[r0,#0]
;;;997 }
0004e2 4770 BX lr
;;;998
ENDP
TIM_SelectCCDMA PROC
;;;1014
;;;1015 tmpcr2 = TIMx->CR2;
0004e4 8882 LDRH r2,[r0,#4]
;;;1016
;;;1017 if (Newstate != DISABLE)
0004e6 b111 CBZ r1,|L1.1262|
;;;1018 {
;;;1019 /* Set the CCDS Bit */
;;;1020 tmpcr2 |= CR2_CCDS_Set;
0004e8 f042f042 ORR r1,r2,#8
0004ec e001 B |L1.1266|
|L1.1262|
;;;1021 }
;;;1022 else
;;;1023 {
;;;1024 /* Reset the CCDS Bit */
;;;1025 tmpcr2 &= CR2_CCDS_Reset;
0004ee f002f002 AND r1,r2,#7
|L1.1266|
;;;1026 }
;;;1027
;;;1028 TIMx->CR2 = (u16)tmpcr2;
0004f2 8081 STRH r1,[r0,#4]
;;;1029 }
0004f4 4770 BX lr
;;;1030
ENDP
TIM_OC1PreloadConfig PROC
;;;1049
;;;1050 tmpccmr1 = TIMx->CCMR1;
0004f6 8b02 LDRH r2,[r0,#0x18]
;;;1051
;;;1052 /* Reset the OCPE Bit */
;;;1053 tmpccmr1 &= CCMR_OC13PE_Mask;
0004f8 f647f647 MOV r3,#0x7f77
0004fc 401a ANDS r2,r2,r3
;;;1054
;;;1055 /* Enable or Disable the Output Compare Preload feature */
;;;1056 tmpccmr1 |= TIM_OCPreload;
0004fe 4311 ORRS r1,r1,r2
;;;1057
;;;1058 TIMx->CCMR1 = (u16)tmpccmr1;
000500 8301 STRH r1,[r0,#0x18]
;;;1059 }
000502 4770 BX lr
;;;1060
ENDP
TIM_OC2PreloadConfig PROC
;;;1079
;;;1080 tmpccmr1 = TIMx->CCMR1;
000504 8b02 LDRH r2,[r0,#0x18]
;;;1081
;;;1082 /* Reset the OCPE Bit */
;;;1083 tmpccmr1 &= CCMR_OC24PE_Mask;
000506 f247f247 MOV r3,#0x777f
00050a 401a ANDS r2,r2,r3
;;;1084
;;;1085 /* Enable or Disable the Output Compare Preload feature */
;;;1086 tmpccmr1 |= (u16)(TIM_OCPreload << 8);
00050c ea42ea42 ORR r1,r2,r1,LSL #8
;;;1087
;;;1088 TIMx->CCMR1 = (u16)tmpccmr1;
000510 8301 STRH r1,[r0,#0x18]
;;;1089 }
000512 4770 BX lr
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