📄 stm32f10x_tim.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 914] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\rvmdk\stm32f10x_tim.o --depend=.\rvmdk\stm32f10x_tim.d --device=DARMSTM -O1 -Otime -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -I..\..\..\..\..\uC-Probe\Target\Plugins\uCOS-II -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\Source -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Ports\ST\STM32 -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Source -ID:\Keil\ARM\INC\ST\STM32F10x ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_tim.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
TIM_DeInit PROC
;;;124 void TIM_DeInit(TIM_TypeDef* TIMx)
;;;125 {
000000 b510 PUSH {r4,lr}
;;;126 switch (*(u32*)&TIMx)
000002 f1b0f1b0 CMP r0,#0x40000000
000006 d011 BEQ |L1.44|
000008 f1a0f1a0 SUB r0,r0,#0x40000000
00000c f5b0f5b0 SUBS r0,r0,#0x400
000010 d016 BEQ |L1.64|
000012 f5b0f5b0 CMP r0,#0x400
000016 d11d BNE |L1.84|
000018 2101 MOVS r1,#1
00001a 2004 MOVS r0,#4
00001c f7fff7ff BL RCC_APB1PeriphResetCmd
000020 2100 MOVS r1,#0
000022 e8bde8bd POP {r4,lr}
000026 2004 MOVS r0,#4
000028 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.44|
;;;127 {
;;;128 case TIM2_BASE:
;;;129 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
00002c 2101 MOVS r1,#1
00002e 4608 MOV r0,r1
000030 f7fff7ff BL RCC_APB1PeriphResetCmd
;;;130 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
000034 2100 MOVS r1,#0
000036 e8bde8bd POP {r4,lr}
00003a 2001 MOVS r0,#1
00003c f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.64|
;;;131 break;
;;;132
;;;133 case TIM3_BASE:
;;;134 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
000040 2101 MOVS r1,#1
000042 2002 MOVS r0,#2
000044 f7fff7ff BL RCC_APB1PeriphResetCmd
;;;135 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
000048 2100 MOVS r1,#0
00004a e8bde8bd POP {r4,lr}
00004e 2002 MOVS r0,#2
000050 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.84|
;;;136 break;
;;;137
;;;138 case TIM4_BASE:
;;;139 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
;;;140 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
;;;141 break;
;;;142
;;;143 default:
;;;144 break;
;;;145 }
;;;146 }
000054 bd10 POP {r4,pc}
;;;147
ENDP
TIM_TimeBaseInit PROC
;;;165 /* Set the Autoreload value */
;;;166 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
000056 880a LDRH r2,[r1,#0]
000058 8582 STRH r2,[r0,#0x2c]
;;;167
;;;168 /* Set the Prescaler value */
;;;169 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
00005a 884a LDRH r2,[r1,#2]
00005c 8502 STRH r2,[r0,#0x28]
;;;170
;;;171 /* Select the Counter Mode and set the clock division */
;;;172 TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
00005e 8802 LDRH r2,[r0,#0]
000060 f002f002 AND r2,r2,#0x9f
000064 8002 STRH r2,[r0,#0]
;;;173 TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision |
000066 888a LDRH r2,[r1,#4]
000068 88c9 LDRH r1,[r1,#6]
00006a 4311 ORRS r1,r1,r2
00006c 8802 LDRH r2,[r0,#0]
00006e 4311 ORRS r1,r1,r2
000070 8001 STRH r1,[r0,#0]
;;;174 TIM_TimeBaseInitStruct->TIM_CounterMode;
;;;175 }
000072 4770 BX lr
;;;176 /*******************************************************************************
ENDP
TIM_OCInit PROC
;;;187 void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
;;;188 {
000074 b430 PUSH {r4,r5}
;;;189 u32 tmpccmrx = 0, tmpccer = 0;
;;;190
;;;191 /* Check the parameters */
;;;192 assert(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;193 assert(IS_TIM_CHANNEL(TIM_OCInitStruct->TIM_Channel));
;;;194 assert(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
;;;195
;;;196 tmpccer = TIMx->CCER;
000076 8c03 LDRH r3,[r0,#0x20]
;;;197
;;;198 if ((TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_1) ||
000078 884a LDRH r2,[r1,#2]
00007a 4dfa LDR r5,|L1.1124|
00007c 4cfa LDR r4,|L1.1128|
00007e b10a CBZ r2,|L1.132|
;;;199 (TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_2))
000080 2a01 CMP r2,#1
000082 d12b BNE |L1.220|
|L1.132|
;;;200 {
;;;201 tmpccmrx = TIMx->CCMR1;
000084 f8b0f8b0 LDRH r12,[r0,#0x18]
;;;202
;;;203 /* Reset the Output Compare Bits */
;;;204 tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel];
000088 f835f835 LDRH r5,[r5,r2,LSL #1]
00008c ea05ea05 AND r12,r5,r12
;;;205
;;;206 /* Set the Output Polarity level */
;;;207 tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel];
000090 f834f834 LDRH r4,[r4,r2,LSL #1]
000094 4023 ANDS r3,r3,r4
;;;208
;;;209 if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_1)
000096 b97a CBNZ r2,|L1.184|
;;;210 {
;;;211 /* Disable the Channel 1: Reset the CCE Bit */
;;;212 TIMx->CCER &= CCER_CC1E_Reset;
000098 8c02 LDRH r2,[r0,#0x20]
00009a f022f022 BIC r2,r2,#1
00009e 8402 STRH r2,[r0,#0x20]
;;;213
;;;214 /* Select the Output Compare Mode */
;;;215 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
0000a0 880a LDRH r2,[r1,#0]
0000a2 ea42ea42 ORR r2,r2,r12
;;;216
;;;217 /* Set the Capture Compare Register value */
;;;218 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
0000a6 f8b1f8b1 LDRH r12,[r1,#4]
0000aa f8a0f8a0 STRH r12,[r0,#0x34]
;;;219
;;;220 /* Set the Capture Compare Enable Bit */
;;;221 tmpccer |= CCER_CC1E_Set;
0000ae f043f043 ORR r3,r3,#1
;;;222
;;;223 /* Set the Capture Compare Polarity */
;;;224 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
0000b2 88c9 LDRH r1,[r1,#6]
0000b4 430b ORRS r3,r3,r1
0000b6 e00f B |L1.216|
|L1.184|
;;;225 }
;;;226 else /* TIM_Channel_2 */
;;;227 {
;;;228 /* Disable the Channel 2: Reset the CCE Bit */
;;;229 TIMx->CCER &= CCER_CC2E_Reset;
0000b8 8c02 LDRH r2,[r0,#0x20]
0000ba f022f022 BIC r2,r2,#0x10
0000be 8402 STRH r2,[r0,#0x20]
;;;230
;;;231 /* Select the Output Compare Mode */
;;;232 tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8;
0000c0 880a LDRH r2,[r1,#0]
0000c2 ea4cea4c ORR r2,r12,r2,LSL #8
;;;233
;;;234 /* Set the Capture Compare Register value */
;;;235 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
0000c6 f8b1f8b1 LDRH r12,[r1,#4]
0000ca f8a0f8a0 STRH r12,[r0,#0x38]
;;;236
;;;237 /* Set the Capture Compare Enable Bit */
;;;238 tmpccer |= CCER_CC2E_Set;
0000ce f043f043 ORR r3,r3,#0x10
;;;239
;;;240 /* Set the Capture Compare Polarity */
;;;241 tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 4;
0000d2 88c9 LDRH r1,[r1,#6]
0000d4 ea43ea43 ORR r3,r3,r1,LSL #4
|L1.216|
;;;242 }
;;;243
;;;244 TIMx->CCMR1 = (u16)tmpccmrx;
0000d8 8302 STRH r2,[r0,#0x18]
0000da e030 B |L1.318|
|L1.220|
;;;245 }
;;;246 else
;;;247 {
;;;248 if ((TIM_OCInitStruct->TIM_Channel == TIM_Channel_3) ||
0000dc 2a02 CMP r2,#2
0000de d001 BEQ |L1.228|
;;;249 (TIM_OCInitStruct->TIM_Channel == TIM_Channel_4))
0000e0 2a03 CMP r2,#3
0000e2 d12c BNE |L1.318|
|L1.228|
;;;250 {
;;;251 tmpccmrx = TIMx->CCMR2;
0000e4 f8b0f8b0 LDRH r12,[r0,#0x1c]
;;;252
;;;253 /* Reset the Output Compare Bits */
;;;254 tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel];
0000e8 f835f835 LDRH r5,[r5,r2,LSL #1]
0000ec ea05ea05 AND r12,r5,r12
;;;255
;;;256 /* Set the Output Polarity level */
;;;257 tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel];
0000f0 f834f834 LDRH r4,[r4,r2,LSL #1]
0000f4 4023 ANDS r3,r3,r4
;;;258
;;;259 if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_3)
0000f6 2a02 CMP r2,#2
0000f8 d110 BNE |L1.284|
;;;260 {
;;;261 /* Disable the Channel 3: Reset the CCE Bit */
;;;262 TIMx->CCER &= CCER_CC3E_Reset;
0000fa 8c02 LDRH r2,[r0,#0x20]
0000fc f422f422 BIC r2,r2,#0x100
000100 8402 STRH r2,[r0,#0x20]
;;;263
;;;264 /* Select the Output Compare Mode */
;;;265 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
000102 880a LDRH r2,[r1,#0]
000104 ea42ea42 ORR r2,r2,r12
;;;266
;;;267 /* Set the Capture Compare Register value */
;;;268 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
000108 f8b1f8b1 LDRH r12,[r1,#4]
00010c f8a0f8a0 STRH r12,[r0,#0x3c]
;;;269
;;;270 /* Set the Capture Compare Enable Bit */
;;;271 tmpccer |= CCER_CC3E_Set;
000110 f443f443 ORR r3,r3,#0x100
;;;272
;;;273 /* Set the Capture Compare Polarity */
;;;274 tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 8;
000114 88c9 LDRH r1,[r1,#6]
000116 ea43ea43 ORR r3,r3,r1,LSL #8
00011a e00f B |L1.316|
|L1.284|
;;;275 }
;;;276 else /* TIM_Channel_4 */
;;;277 {
;;;278 /* Disable the Channel 4: Reset the CCE Bit */
;;;279 TIMx->CCER &= CCER_CC4E_Reset;
00011c 8c02 LDRH r2,[r0,#0x20]
00011e f422f422 BIC r2,r2,#0x1000
000122 8402 STRH r2,[r0,#0x20]
;;;280
;;;281 /* Select the Output Compare Mode */
;;;282 tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8;
000124 880a LDRH r2,[r1,#0]
000126 ea4cea4c ORR r2,r12,r2,LSL #8
;;;283
;;;284 /* Set the Capture Compare Register value */
;;;285 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
00012a f8b1f8b1 LDRH r12,[r1,#4]
00012e f8a0f8a0 STRH r12,[r0,#0x40]
;;;286
;;;287 /* Set the Capture Compare Enable Bit */
;;;288 tmpccer |= CCER_CC4E_Set;
000132 f443f443 ORR r3,r3,#0x1000
;;;289
;;;290 /* Set the Capture Compare Polarity */
;;;291 tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 12;
000136 88c9 LDRH r1,[r1,#6]
000138 ea43ea43 ORR r3,r3,r1,LSL #12
|L1.316|
;;;292 }
;;;293
;;;294 TIMx->CCMR2 = (u16)tmpccmrx;
00013c 8382 STRH r2,[r0,#0x1c]
|L1.318|
;;;295 }
;;;296 }
;;;297
;;;298 TIMx->CCER = (u16)tmpccer;
00013e 8403 STRH r3,[r0,#0x20]
;;;299 }
000140 bc30 POP {r4,r5}
000142 4770 BX lr
;;;300
ENDP
TIM_SetIC1Prescaler PROC
;;;1890
;;;1891 tmpccmr1 = TIMx->CCMR1;
000144 8b02 LDRH r2,[r0,#0x18]
;;;1892
;;;1893 /* Reset the IC1PSC Bits */
;;;1894 tmpccmr1 &= CCMR_IC13PSC_Mask;
000146 f64ff64f MOV r3,#0xfff3
00014a 401a ANDS r2,r2,r3
;;;1895
;;;1896 /* Set the IC1PSC value */
;;;1897 tmpccmr1 |= TIM_IC1Prescaler;
00014c 4311 ORRS r1,r1,r2
;;;1898
;;;1899 TIMx->CCMR1 = (u16)tmpccmr1;
00014e 8301 STRH r1,[r0,#0x18]
;;;1900 }
000150 4770 BX lr
;;;1901
ENDP
TI1_Config PROC
;;;2324 u8 TIM_ICFilter)
;;;2325 {
000152 b430 PUSH {r4,r5}
;;;2326 u32 tmpccmr1 = 0, tmpccer = 0;
;;;2327
;;;2328 tmpccmr1 = TIMx->CCMR1;
000154 8b04 LDRH r4,[r0,#0x18]
;;;2329 tmpccer = TIMx->CCER;
000156 f8b0f8b0 LDRH r12,[r0,#0x20]
;;;2330
;;;2331 /* Disable the Channel 1: Reset the CCE Bit */
;;;2332 TIMx->CCER &= CCER_CC1E_Reset;
00015a 8c05 LDRH r5,[r0,#0x20]
00015c f025f025 BIC r5,r5,#1
000160 8405 STRH r5,[r0,#0x20]
;;;2333
;;;2334 /* Select the Input and set the filter */
;;;2335 tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
000162 f647f647 MOV r5,#0x7f0c
000166 402c ANDS r4,r4,r5
;;;2336 tmpccmr1 |= TIM_ICSelection | (u16)((u16)TIM_ICFilter << 4);
000168 ea42ea42 ORR r2,r2,r3,LSL #4
00016c 4322 ORRS r2,r2,r4
;;;2337
;;;2338 /* Select the Polarity and set the CCE Bit */
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