stm32f10x_dma.txt

ucos2.86版本结合STM板极支持包

; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 914] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\rvmdk\stm32f10x_dma.o --depend=.\rvmdk\stm32f10x_dma.d --device=DARMSTM -O1 -Otime -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -I..\..\..\..\..\uC-Probe\Target\Plugins\uCOS-II -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\Source -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Ports\ST\STM32 -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Source -ID:\Keil\ARM\INC\ST\STM32F10x ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_dma.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  DMA_Cmd PROC
;;;236    
;;;237      if (NewState != DISABLE)				  
000000  b121              CBZ      r1,|L1.12|
;;;238      {
;;;239        /* Enable the selected DMA Channelx */
;;;240        DMA_Channelx->CCR |= CCR_ENABLE_Set;
000002  6801              LDR      r1,[r0,#0]
000004  f041f041          ORR      r1,r1,#1
000008  6001              STR      r1,[r0,#0]
;;;241      }
;;;242      else
;;;243      {
;;;244        /* Disable the selected DMA Channelx */
;;;245        DMA_Channelx->CCR &= CCR_ENABLE_Reset;
;;;246      }
;;;247    }
00000a  4770              BX       lr
                  |L1.12|
00000c  6801              LDR      r1,[r0,#0]
00000e  f021f021          BIC      r1,r1,#1
000012  6001              STR      r1,[r0,#0]
000014  4770              BX       lr
;;;248    
                          ENDP

                  DMA_DeInit PROC
;;;57     void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx)
;;;58     {
000016  b500              PUSH     {lr}
000018  4602              MOV      r2,r0
;;;59       /* DMA Channelx disable */
;;;60       DMA_Cmd(DMA_Channelx, DISABLE);
00001a  2100              MOVS     r1,#0
00001c  4610              MOV      r0,r2
00001e  f7fff7ff          BL       DMA_Cmd
;;;61     
;;;62       /* Reset Channelx control register */
;;;63       DMA_Channelx->CCR  = 0;
000022  2000              MOVS     r0,#0
000024  6010              STR      r0,[r2,#0]
;;;64       
;;;65       /* Reset Channelx remaining bytes register */
;;;66       DMA_Channelx->CNDTR = 0;
000026  6050              STR      r0,[r2,#4]
;;;67       
;;;68       /* Reset Channelx peripheral address register */
;;;69       DMA_Channelx->CPAR  = 0;
000028  6090              STR      r0,[r2,#8]
;;;70       
;;;71       /* Reset Channelx memory address register */
;;;72       DMA_Channelx->CMAR = 0;
00002a  60d0              STR      r0,[r2,#0xc]
;;;73     
;;;74       switch (*(u32*)&DMA_Channelx)
00002c  4b47              LDR      r3,|L1.332|
00002e  4948              LDR      r1,|L1.336|
000030  1ad0              SUBS     r0,r2,r3
000032  429a              CMP      r2,r3
000034  d021              BEQ      |L1.122|
000036  dc0b              BGT      |L1.80|
000038  4846              LDR      r0,|L1.340|
00003a  1810              ADDS     r0,r2,r0
00003c  d013              BEQ      |L1.102|
00003e  2814              CMP      r0,#0x14
000040  d016              BEQ      |L1.112|
000042  2828              CMP      r0,#0x28
000044  d103              BNE      |L1.78|
;;;75       {
;;;76         case DMA_Channel1_BASE:
;;;77           /* Reset interrupt pending bits for Channel1 */
;;;78           DMA->IFCR |= DMA_Channel1_IT_Mask;
;;;79           break;
;;;80     
;;;81         case DMA_Channel2_BASE:
;;;82           /* Reset interrupt pending bits for Channel2 */
;;;83           DMA->IFCR |= DMA_Channel2_IT_Mask;
;;;84           break;
;;;85     
;;;86         case DMA_Channel3_BASE:
;;;87           /* Reset interrupt pending bits for Channel3 */
;;;88           DMA->IFCR |= DMA_Channel3_IT_Mask;
000046  6848              LDR      r0,[r1,#4]
000048  f440f440          ORR      r0,r0,#0xf00
00004c  6048              STR      r0,[r1,#4]
                  |L1.78|
;;;89           break;
;;;90     
;;;91         case DMA_Channel4_BASE:
;;;92           /* Reset interrupt pending bits for Channel4 */
;;;93           DMA->IFCR |= DMA_Channel4_IT_Mask;
;;;94           break;
;;;95     
;;;96         case DMA_Channel5_BASE:
;;;97           /* Reset interrupt pending bits for Channel5 */
;;;98           DMA->IFCR |= DMA_Channel5_IT_Mask;
;;;99           break;
;;;100    
;;;101        case DMA_Channel6_BASE:
;;;102          /* Reset interrupt pending bits for Channel6 */
;;;103          DMA->IFCR |= DMA_Channel6_IT_Mask;
;;;104          break;
;;;105    
;;;106        case DMA_Channel7_BASE:
;;;107          /* Reset interrupt pending bits for Channel7 */
;;;108          DMA->IFCR |= DMA_Channel7_IT_Mask;
;;;109          break;
;;;110    
;;;111        default:
;;;112          break;
;;;113      }
;;;114    }
00004e  bd00              POP      {pc}
                  |L1.80|
000050  2814              CMP      r0,#0x14
000052  d017              BEQ      |L1.132|
000054  2828              CMP      r0,#0x28
000056  d01a              BEQ      |L1.142|
000058  283c              CMP      r0,#0x3c
00005a  d1f8              BNE      |L1.78|
00005c  6848              LDR      r0,[r1,#4]
00005e  f040f040          ORR      r0,r0,#0xf000000
000062  6048              STR      r0,[r1,#4]
000064  bd00              POP      {pc}
                  |L1.102|
000066  6848              LDR      r0,[r1,#4]
000068  f040f040          ORR      r0,r0,#0xf
00006c  6048              STR      r0,[r1,#4]
00006e  bd00              POP      {pc}
                  |L1.112|
000070  6848              LDR      r0,[r1,#4]
000072  f040f040          ORR      r0,r0,#0xf0
000076  6048              STR      r0,[r1,#4]
000078  bd00              POP      {pc}
                  |L1.122|
00007a  6848              LDR      r0,[r1,#4]
00007c  f440f440          ORR      r0,r0,#0xf000
000080  6048              STR      r0,[r1,#4]
000082  bd00              POP      {pc}
                  |L1.132|
000084  6848              LDR      r0,[r1,#4]
000086  f440f440          ORR      r0,r0,#0xf0000
00008a  6048              STR      r0,[r1,#4]
00008c  bd00              POP      {pc}
                  |L1.142|
00008e  6848              LDR      r0,[r1,#4]
000090  f440f440          ORR      r0,r0,#0xf00000
000094  6048              STR      r0,[r1,#4]
000096  bd00              POP      {pc}
;;;115    
                          ENDP

                  DMA_Init PROC
;;;128    void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct)
;;;129    {
000098  b410              PUSH     {r4}
;;;130      u32 tmpreg = 0;
;;;131    
;;;132      /* Check the parameters */
;;;133      assert(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
;;;134      assert(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));	   
;;;135      assert(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));  
;;;136      assert(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));   
;;;137      assert(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
;;;138      assert(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
;;;139      assert(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
;;;140      assert(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
;;;141      assert(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
;;;142    
;;;143    /*--------------------------- DMA Channelx CCR Configuration -----------------*/
;;;144      /* Get the DMA_Channelx CCR value */
;;;145      tmpreg = DMA_Channelx->CCR;
00009a  6802              LDR      r2,[r0,#0]
;;;146      /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRCULAR and DIR bits */
;;;147      tmpreg &= CCR_CLEAR_Mask;
00009c  f36ff36f          BFC      r2,#4,#11
;;;148      /* Configure DMA Channelx: data transfer, data size, priority level and mode */
;;;149      /* Set DIR bit according to DMA_DIR value */
;;;150      /* Set CIRCULAR bit according to DMA_Mode value */
;;;151      /* Set PINC bit according to DMA_PeripheralInc value */
;;;152      /* Set MINC bit according to DMA_MemoryInc value */
;;;153      /* Set PSIZE bits according to DMA_PeripheralDataSize value */
;;;154      /* Set MSIZE bits according to DMA_MemoryDataSize value */
;;;155      /* Set PL bits according to DMA_Priority value */
;;;156      /* Set the MEM2MEM bit according to DMA_M2M value */
;;;157      tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
0000a0  f8d1f8d1          LDR      r12,[r1,#0x20]
0000a4  688b              LDR      r3,[r1,#8]
0000a6  694c              LDR      r4,[r1,#0x14]
0000a8  ea43ea43          ORR      r3,r3,r12
0000ac  f8d1f8d1          LDR      r12,[r1,#0x10]
0000b0  ea4cea4c          ORR      r12,r12,r4
0000b4  ea43ea43          ORR      r3,r3,r12
0000b8  f8d1f8d1          LDR      r12,[r1,#0x18]
0000bc  ea43ea43          ORR      r3,r3,r12
0000c0  f8d1f8d1          LDR      r12,[r1,#0x1c]
0000c4  ea43ea43          ORR      r3,r3,r12
0000c8  f8d1f8d1          LDR      r12,[r1,#0x24]
0000cc  ea43ea43          ORR      r3,r3,r12
0000d0  f8d1f8d1          LDR      r12,[r1,#0x28]
0000d4  ea43ea43          ORR      r3,r3,r12
0000d8  431a              ORRS     r2,r2,r3
;;;158                DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
;;;159                DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |