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📄 stm32f10x_rcc.txt

📁 ucos2.86版本结合STM板极支持包
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;;;728      tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
0001f0  6851              LDR      r1,[r2,#4]
0001f2  f001f001          AND      r1,r1,#0xf0
;;;729      tmp = tmp >> 4;
0001f6  0909              LSRS     r1,r1,#4
;;;730      presc = APBAHBPrescTable[tmp];
0001f8  f8dff8df          LDR      r12,|L1.772|
0001fc  f81cf81c          LDRB     r1,[r12,r1]
;;;731    
;;;732      /* HCLK clock frequency */
;;;733      RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
000200  6803              LDR      r3,[r0,#0]
000202  fa23fa23          LSR      r1,r3,r1
000206  6041              STR      r1,[r0,#4]
;;;734    
;;;735      /* Get PCLK1 prescaler */
;;;736      tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
000208  6853              LDR      r3,[r2,#4]
00020a  f403f403          AND      r3,r3,#0x700
;;;737      tmp = tmp >> 8;
00020e  0a1b              LSRS     r3,r3,#8
;;;738      presc = APBAHBPrescTable[tmp];
000210  f81cf81c          LDRB     r3,[r12,r3]
;;;739    
;;;740      /* PCLK1 clock frequency */
;;;741      RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
000214  fa21fa21          LSR      r3,r1,r3
000218  6083              STR      r3,[r0,#8]
;;;742    
;;;743      /* Get PCLK2 prescaler */
;;;744      tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
00021a  6853              LDR      r3,[r2,#4]
00021c  f403f403          AND      r3,r3,#0x3800
;;;745      tmp = tmp >> 11;
000220  0adb              LSRS     r3,r3,#11
;;;746      presc = APBAHBPrescTable[tmp];
000222  f81cf81c          LDRB     r3,[r12,r3]
;;;747    
;;;748      /* PCLK2 clock frequency */
;;;749      RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
000226  40d9              LSRS     r1,r1,r3
000228  60c1              STR      r1,[r0,#0xc]
;;;750    
;;;751      /* Get ADCCLK prescaler */
;;;752      tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
00022a  6852              LDR      r2,[r2,#4]
00022c  f402f402          AND      r2,r2,#0xc000
;;;753      tmp = tmp >> 14;
000230  0b92              LSRS     r2,r2,#14
;;;754      presc = ADCPrescTable[tmp];
000232  4b35              LDR      r3,|L1.776|
000234  5c9a              LDRB     r2,[r3,r2]
;;;755    
;;;756      /* ADCCLK clock frequency */
;;;757      RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
000236  fbb1fbb1          UDIV     r1,r1,r2
00023a  6101              STR      r1,[r0,#0x10]
;;;758    }
00023c  bc10              POP      {r4}
00023e  4770              BX       lr
;;;759    
                          ENDP

                  RCC_AHBPeriphClockCmd PROC
;;;779    
;;;780      if (NewState != DISABLE)
000240  4a28              LDR      r2,|L1.740|
000242  b119              CBZ      r1,|L1.588|
;;;781      {
;;;782        RCC->AHBENR |= RCC_AHBPeriph;
000244  6951              LDR      r1,[r2,#0x14]
000246  4308              ORRS     r0,r0,r1
000248  6150              STR      r0,[r2,#0x14]
;;;783      }
;;;784      else
;;;785      {
;;;786        RCC->AHBENR &= ~RCC_AHBPeriph;
;;;787      }
;;;788    }
00024a  4770              BX       lr
                  |L1.588|
00024c  6951              LDR      r1,[r2,#0x14]
00024e  ea21ea21          BIC      r0,r1,r0
000252  6150              STR      r0,[r2,#0x14]
000254  4770              BX       lr
;;;789    
                          ENDP

                  RCC_APB2PeriphClockCmd PROC
;;;810    
;;;811      if (NewState != DISABLE)
000256  4a23              LDR      r2,|L1.740|
000258  b119              CBZ      r1,|L1.610|
;;;812      {
;;;813        RCC->APB2ENR |= RCC_APB2Periph;
00025a  6991              LDR      r1,[r2,#0x18]
00025c  4308              ORRS     r0,r0,r1
00025e  6190              STR      r0,[r2,#0x18]
;;;814      }
;;;815      else
;;;816      {
;;;817        RCC->APB2ENR &= ~RCC_APB2Periph;
;;;818      }
;;;819    }
000260  4770              BX       lr
                  |L1.610|
000262  6991              LDR      r1,[r2,#0x18]
000264  ea21ea21          BIC      r0,r1,r0
000268  6190              STR      r0,[r2,#0x18]
00026a  4770              BX       lr
;;;820    
                          ENDP

                  RCC_APB1PeriphClockCmd PROC
;;;842    
;;;843      if (NewState != DISABLE)
00026c  4a1d              LDR      r2,|L1.740|
00026e  b119              CBZ      r1,|L1.632|
;;;844      {
;;;845        RCC->APB1ENR |= RCC_APB1Periph;
000270  69d1              LDR      r1,[r2,#0x1c]
000272  4308              ORRS     r0,r0,r1
000274  61d0              STR      r0,[r2,#0x1c]
;;;846      }
;;;847      else
;;;848      {
;;;849        RCC->APB1ENR &= ~RCC_APB1Periph;
;;;850      }
;;;851    }
000276  4770              BX       lr
                  |L1.632|
000278  69d1              LDR      r1,[r2,#0x1c]
00027a  ea21ea21          BIC      r0,r1,r0
00027e  61d0              STR      r0,[r2,#0x1c]
000280  4770              BX       lr
;;;852    
                          ENDP

                  RCC_APB2PeriphResetCmd PROC
;;;872    
;;;873      if (NewState != DISABLE)
000282  4a18              LDR      r2,|L1.740|
000284  b119              CBZ      r1,|L1.654|
;;;874      {
;;;875        RCC->APB2RSTR |= RCC_APB2Periph;
000286  68d1              LDR      r1,[r2,#0xc]
000288  4308              ORRS     r0,r0,r1
00028a  60d0              STR      r0,[r2,#0xc]
;;;876      }
;;;877      else
;;;878      {
;;;879        RCC->APB2RSTR &= ~RCC_APB2Periph;
;;;880      }
;;;881    }
00028c  4770              BX       lr
                  |L1.654|
00028e  68d1              LDR      r1,[r2,#0xc]
000290  ea21ea21          BIC      r0,r1,r0
000294  60d0              STR      r0,[r2,#0xc]
000296  4770              BX       lr
;;;882    
                          ENDP

                  RCC_APB1PeriphResetCmd PROC
;;;903    
;;;904      if (NewState != DISABLE)
000298  4a12              LDR      r2,|L1.740|
00029a  b119              CBZ      r1,|L1.676|
;;;905      {
;;;906        RCC->APB1RSTR |= RCC_APB1Periph;
00029c  6911              LDR      r1,[r2,#0x10]
00029e  4308              ORRS     r0,r0,r1
0002a0  6110              STR      r0,[r2,#0x10]
;;;907      }
;;;908      else
;;;909      {
;;;910        RCC->APB1RSTR &= ~RCC_APB1Periph;
;;;911      }
;;;912    }
0002a2  4770              BX       lr
                  |L1.676|
0002a4  6911              LDR      r1,[r2,#0x10]
0002a6  ea21ea21          BIC      r0,r1,r0
0002aa  6110              STR      r0,[r2,#0x10]
0002ac  4770              BX       lr
;;;913    
                          ENDP

                  RCC_BackupResetCmd PROC
;;;926    
;;;927      *(vu32 *) BDCR_BDRST_BB = (u32)NewState;
0002ae  4917              LDR      r1,|L1.780|
0002b0  6008              STR      r0,[r1,#0]
;;;928    }
0002b2  4770              BX       lr
;;;929    
                          ENDP

                  RCC_ClockSecuritySystemCmd PROC
;;;942    
;;;943      *(vu32 *) CR_CSSON_BB = (u32)NewState;
0002b4  490d              LDR      r1,|L1.748|
0002b6  64c8              STR      r0,[r1,#0x4c]
;;;944    }
0002b8  4770              BX       lr
;;;945    
                          ENDP

                  RCC_MCOConfig PROC
;;;964      /* Perform Byte access to MCO[26:24] bits to select the MCO source */
;;;965      *(vu8 *) 0x40021007 = RCC_MCO;
0002ba  490a              LDR      r1,|L1.740|
0002bc  71c8              STRB     r0,[r1,#7]
;;;966    }
0002be  4770              BX       lr
;;;967    
                          ENDP

                  RCC_ClearFlag PROC
;;;1040     /* Set RMVF bit to clear the reset flags */
;;;1041     RCC->CSR |= CSR_RMVF_Set;
0002c0  4808              LDR      r0,|L1.740|
0002c2  6a41              LDR      r1,[r0,#0x24]
0002c4  f041f041          ORR      r1,r1,#0x1000000
0002c8  6241              STR      r1,[r0,#0x24]
;;;1042   }
0002ca  4770              BX       lr
;;;1043   
                          ENDP

                  RCC_GetITStatus PROC
;;;1058   ITStatus RCC_GetITStatus(u8 RCC_IT)
;;;1059   {
0002cc  4601              MOV      r1,r0
;;;1060     ITStatus bitstatus = RESET;
0002ce  2000              MOVS     r0,#0
;;;1061   
;;;1062     /* Check the parameters */
;;;1063     assert(IS_RCC_GET_IT(RCC_IT));
;;;1064   
;;;1065     /* Check the status of the specified RCC interrupt */
;;;1066     if ((RCC->CIR & RCC_IT) != (u32)RESET)
0002d0  4a04              LDR      r2,|L1.740|
0002d2  6892              LDR      r2,[r2,#8]
0002d4  420a              TST      r2,r1
0002d6  d000              BEQ      |L1.730|
;;;1067     {
;;;1068       bitstatus = SET;
0002d8  2001              MOVS     r0,#1
                  |L1.730|
;;;1069     }
;;;1070     else
;;;1071     {
;;;1072       bitstatus = RESET;
;;;1073     }
;;;1074   
;;;1075     /* Return the RCC_IT status */
;;;1076     return  bitstatus;
;;;1077   }
0002da  4770              BX       lr
;;;1078   
                          ENDP

                  RCC_ClearITPendingBit PROC
;;;1099        pending bits */
;;;1100     *(vu8 *) 0x4002100A = RCC_IT;
0002dc  4901              LDR      r1,|L1.740|
0002de  7288              STRB     r0,[r1,#0xa]
;;;1101   }
0002e0  4770              BX       lr
;;;1102   
                          ENDP

0002e2  0000              DCW      0x0000
                  |L1.740|
0002e4  40021000          DCD      0x40021000
                  |L1.744|
0002e8  f8ff0000          DCD      0xf8ff0000
                  |L1.748|
0002ec  42420000          DCD      0x42420000
                  |L1.752|
0002f0  424200d8          DCD      0x424200d8
                  |L1.756|
0002f4  42420480          DCD      0x42420480
                  |L1.760|
0002f8  4242043c          DCD      0x4242043c
                  |L1.764|
0002fc  007a1200          DCD      0x007a1200
                  |L1.768|
000300  003d0900          DCD      0x003d0900
                  |L1.772|
000304  00000000          DCD      APBAHBPrescTable
                  |L1.776|
000308  00000000          DCD      ADCPrescTable
                  |L1.780|
00030c  42420440          DCD      0x42420440

                          AREA ||.constdata||, DATA, READONLY, ALIGN=0

                  ADCPrescTable
000000  02040608          DCB      0x02,0x04,0x06,0x08
                  APBAHBPrescTable
000004  00000000          DCB      0x00,0x00,0x00,0x00
000008  01020304          DCB      0x01,0x02,0x03,0x04
00000c  01020304          DCB      0x01,0x02,0x03,0x04
000010  06070809          DCB      0x06,0x07,0x08,0x09

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