📄 stm32f10x_rcc.txt
字号:
;;;362 }
0000fa 4770 BX lr
;;;363
ENDP
RCC_GetSYSCLKSource PROC
;;;376 {
;;;377 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
0000fc 4879 LDR r0,|L1.740|
0000fe 6840 LDR r0,[r0,#4]
000100 f000f000 AND r0,r0,#0xc
;;;378 }
000104 4770 BX lr
;;;379
ENDP
RCC_HCLKConfig PROC
;;;404
;;;405 tmpreg = RCC->CFGR;
000106 4a77 LDR r2,|L1.740|
000108 6851 LDR r1,[r2,#4]
;;;406
;;;407 /* Clear HPRE[7:4] bits */
;;;408 tmpreg &= CFGR_HPRE_Reset_Mask;
00010a f021f021 BIC r1,r1,#0xf0
;;;409
;;;410 /* Set HPRE[7:4] bits according to RCC_HCLK value */
;;;411 tmpreg |= RCC_HCLK;
00010e 4308 ORRS r0,r0,r1
;;;412
;;;413 /* Store the new value */
;;;414 RCC->CFGR = tmpreg;
000110 6050 STR r0,[r2,#4]
;;;415 }
000112 4770 BX lr
;;;416
ENDP
RCC_PCLK1Config PROC
;;;437
;;;438 tmpreg = RCC->CFGR;
000114 4a73 LDR r2,|L1.740|
000116 6851 LDR r1,[r2,#4]
;;;439
;;;440 /* Clear PPRE1[10:8] bits */
;;;441 tmpreg &= CFGR_PPRE1_Reset_Mask;
000118 f421f421 BIC r1,r1,#0x700
;;;442
;;;443 /* Set PPRE1[10:8] bits according to RCC_PCLK1 value */
;;;444 tmpreg |= RCC_PCLK1;
00011c 4308 ORRS r0,r0,r1
;;;445
;;;446 /* Store the new value */
;;;447 RCC->CFGR = tmpreg;
00011e 6050 STR r0,[r2,#4]
;;;448 }
000120 4770 BX lr
;;;449
ENDP
RCC_PCLK2Config PROC
;;;470
;;;471 tmpreg = RCC->CFGR;
000122 4a70 LDR r2,|L1.740|
000124 6851 LDR r1,[r2,#4]
;;;472
;;;473 /* Clear PPRE2[13:11] bits */
;;;474 tmpreg &= CFGR_PPRE2_Reset_Mask;
000126 f421f421 BIC r1,r1,#0x3800
;;;475
;;;476 /* Set PPRE2[13:11] bits according to RCC_PCLK2 value */
;;;477 tmpreg |= RCC_PCLK2 << 3;
00012a ea41ea41 ORR r0,r1,r0,LSL #3
;;;478
;;;479 /* Store the new value */
;;;480 RCC->CFGR = tmpreg;
00012e 6050 STR r0,[r2,#4]
;;;481 }
000130 4770 BX lr
;;;482
ENDP
RCC_ITConfig PROC
;;;504
;;;505 if (NewState != DISABLE)
000132 4a6c LDR r2,|L1.740|
000134 b119 CBZ r1,|L1.318|
;;;506 {
;;;507 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
;;;508 *(vu8 *) 0x40021009 |= RCC_IT;
000136 7a51 LDRB r1,[r2,#9]
000138 4308 ORRS r0,r0,r1
00013a 7250 STRB r0,[r2,#9]
;;;509 }
;;;510 else
;;;511 {
;;;512 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
;;;513 *(vu8 *) 0x40021009 &= ~(u32)RCC_IT;
;;;514 }
;;;515 }
00013c 4770 BX lr
|L1.318|
00013e 7a51 LDRB r1,[r2,#9]
000140 ea21ea21 BIC r0,r1,r0
000144 7250 STRB r0,[r2,#9]
000146 4770 BX lr
;;;516
ENDP
RCC_USBCLKConfig PROC
;;;534
;;;535 *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
000148 4969 LDR r1,|L1.752|
00014a 6008 STR r0,[r1,#0]
;;;536 }
00014c 4770 BX lr
;;;537
ENDP
RCC_ADCCLKConfig PROC
;;;557
;;;558 tmpreg = RCC->CFGR;
00014e 4a65 LDR r2,|L1.740|
000150 6851 LDR r1,[r2,#4]
;;;559
;;;560 /* Clear ADCPRE[15:14] bits */
;;;561 tmpreg &= CFGR_ADCPRE_Reset_Mask;
000152 f421f421 BIC r1,r1,#0xc000
;;;562
;;;563 /* Set ADCPRE[15:14] bits according to RCC_ADCCLK value */
;;;564 tmpreg |= RCC_ADCCLK;
000156 4308 ORRS r0,r0,r1
;;;565
;;;566 /* Store the new value */
;;;567 RCC->CFGR = tmpreg;
000158 6050 STR r0,[r2,#4]
;;;568 }
00015a 4770 BX lr
;;;569
ENDP
RCC_LSEConfig PROC
;;;588 /* Reset LSEON bit */
;;;589 *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
00015c 4961 LDR r1,|L1.740|
00015e 2200 MOVS r2,#0
000160 f881f881 STRB r2,[r1,#0x20]
;;;590
;;;591 /* Reset LSEBYP bit */
;;;592 *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
000164 f881f881 STRB r2,[r1,#0x20]
;;;593
;;;594 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
;;;595 switch(RCC_LSE)
000168 2801 CMP r0,#1
00016a d005 BEQ |L1.376|
00016c 2804 CMP r0,#4
00016e d102 BNE |L1.374|
;;;596 {
;;;597 case RCC_LSE_ON:
;;;598 /* Set LSEON bit */
;;;599 *(vu8 *) BDCR_BASE = RCC_LSE_ON;
;;;600 break;
;;;601
;;;602 case RCC_LSE_Bypass:
;;;603 /* Set LSEBYP and LSEON bits */
;;;604 *(vu8 *) BDCR_BASE = RCC_LSE_Bypass | RCC_LSE_ON;
000170 2005 MOVS r0,#5
000172 f881f881 STRB r0,[r1,#0x20]
|L1.374|
;;;605 break;
;;;606
;;;607 default:
;;;608 break;
;;;609 }
;;;610 }
000176 4770 BX lr
|L1.376|
000178 2001 MOVS r0,#1
00017a f881f881 STRB r0,[r1,#0x20]
00017e 4770 BX lr
;;;611
ENDP
RCC_LSICmd PROC
;;;625
;;;626 *(vu32 *) CSR_LSION_BB = (u32)NewState;
000180 495c LDR r1,|L1.756|
000182 6008 STR r0,[r1,#0]
;;;627 }
000184 4770 BX lr
;;;628
ENDP
RCC_RTCCLKConfig PROC
;;;648 /* Select the RTC clock source */
;;;649 RCC->BDCR |= RCC_RTCCLKSource;
000186 4957 LDR r1,|L1.740|
000188 6a0a LDR r2,[r1,#0x20]
00018a 4310 ORRS r0,r0,r2
00018c 6208 STR r0,[r1,#0x20]
;;;650 }
00018e 4770 BX lr
;;;651
ENDP
RCC_RTCCLKCmd PROC
;;;666
;;;667 *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
000190 4959 LDR r1,|L1.760|
000192 6008 STR r0,[r1,#0]
;;;668 }
000194 4770 BX lr
;;;669
ENDP
RCC_GetClocksFreq PROC
;;;678 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
;;;679 {
000196 b410 PUSH {r4}
;;;680 u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
;;;681
;;;682 /* Get SYSCLK source -------------------------------------------------------*/
;;;683 tmp = RCC->CFGR & CFGR_SWS_Mask;
000198 4a52 LDR r2,|L1.740|
00019a 6851 LDR r1,[r2,#4]
00019c f001f001 AND r1,r1,#0xc
;;;684
;;;685 switch (tmp)
0001a0 4b56 LDR r3,|L1.764|
0001a2 b1a9 CBZ r1,|L1.464|
0001a4 2904 CMP r1,#4
0001a6 d015 BEQ |L1.468|
0001a8 2908 CMP r1,#8
0001aa d120 BNE |L1.494|
0001ac 6851 LDR r1,[r2,#4]
0001ae f401f401 AND r1,r1,#0x3c0000
0001b2 f04ff04f MOV r12,#2
0001b6 eb0ceb0c ADD r1,r12,r1,LSR #18
0001ba f8d2f8d2 LDR r12,[r2,#4]
0001be f40cf40c AND r12,r12,#0x10000
0001c2 4c4f LDR r4,|L1.768|
0001c4 f1bcf1bc CMP r12,#0
;;;686 {
;;;687 case 0x00: /* HSI used as system clock */
;;;688 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
;;;689 break;
;;;690
;;;691 case 0x04: /* HSE used as system clock */
;;;692 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
;;;693 break;
;;;694
;;;695 case 0x08: /* PLL used as system clock */
;;;696 /* Get PLL clock source and multiplication factor ----------------------*/
;;;697 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
;;;698 pllmull = ( pllmull >> 18) + 2;
;;;699
;;;700 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
;;;701
;;;702 if (pllsource == 0x00)
0001c8 d106 BNE |L1.472|
0001ca 4361 MULS r1,r4,r1
0001cc 6001 STR r1,[r0,#0]
;;;703 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;704 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
0001ce e00f B |L1.496|
|L1.464|
0001d0 6003 STR r3,[r0,#0]
0001d2 e00d B |L1.496|
|L1.468|
0001d4 6003 STR r3,[r0,#0]
0001d6 e00b B |L1.496|
|L1.472|
;;;705 }
;;;706 else
;;;707 {/* HSE selected as PLL clock entry */
;;;708
;;;709 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
0001d8 f8d2f8d2 LDR r12,[r2,#4]
0001dc f41cf41c TST r12,#0x20000
0001e0 d002 BEQ |L1.488|
;;;710 {/* HSE oscillator clock divided by 2 */
;;;711
;;;712 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
0001e2 4361 MULS r1,r4,r1
0001e4 6001 STR r1,[r0,#0]
0001e6 e003 B |L1.496|
|L1.488|
;;;713 }
;;;714 else
;;;715 {
;;;716 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
0001e8 4359 MULS r1,r3,r1
0001ea 6001 STR r1,[r0,#0]
0001ec e000 B |L1.496|
|L1.494|
;;;717 }
;;;718 }
;;;719 break;
;;;720
;;;721 default:
;;;722 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
0001ee 6003 STR r3,[r0,#0]
|L1.496|
;;;723 break;
;;;724 }
;;;725
;;;726 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
;;;727 /* Get HCLK prescaler */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -