📄 stm32f10x_rcc.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 914] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\rvmdk\stm32f10x_rcc.o --depend=.\rvmdk\stm32f10x_rcc.d --device=DARMSTM -O1 -Otime -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -I..\..\..\..\..\uC-Probe\Target\Plugins\uCOS-II -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\Source -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Ports\ST\STM32 -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Source -ID:\Keil\ARM\INC\ST\STM32F10x ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_rcc.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
RCC_DeInit PROC
;;;126 /* Disable APB2 Peripheral Reset */
;;;127 RCC->APB2RSTR = 0x00000000;
000000 48b8 LDR r0,|L1.740|
000002 2100 MOVS r1,#0
000004 60c1 STR r1,[r0,#0xc]
;;;128
;;;129 /* Disable APB1 Peripheral Reset */
;;;130 RCC->APB1RSTR = 0x00000000;
000006 6101 STR r1,[r0,#0x10]
;;;131
;;;132 /* FLITF and SRAM Clock ON */
;;;133 RCC->AHBENR = 0x00000014;
000008 2214 MOVS r2,#0x14
00000a 6142 STR r2,[r0,#0x14]
;;;134
;;;135 /* Disable APB2 Peripheral Clock */
;;;136 RCC->APB2ENR = 0x00000000;
00000c 6181 STR r1,[r0,#0x18]
;;;137
;;;138 /* Disable APB1 Peripheral Clock */
;;;139 RCC->APB1ENR = 0x00000000;
00000e 61c1 STR r1,[r0,#0x1c]
;;;140
;;;141 /* Set HSION bit */
;;;142 RCC->CR |= (u32)0x00000001;
000010 6802 LDR r2,[r0,#0]
000012 f042f042 ORR r2,r2,#1
000016 6002 STR r2,[r0,#0]
;;;143
;;;144 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits*/
;;;145 RCC->CFGR &= 0xF8FF0000;
000018 6842 LDR r2,[r0,#4]
00001a 4bb3 LDR r3,|L1.744|
00001c 401a ANDS r2,r2,r3
00001e 6042 STR r2,[r0,#4]
;;;146
;;;147 /* Reset HSEON, CSSON and PLLON bits */
;;;148 RCC->CR &= 0xFEF6FFFF;
000020 6802 LDR r2,[r0,#0]
000022 f422f422 BIC r2,r2,#0x90000
000026 f022f022 BIC r2,r2,#0x1000000
00002a 6002 STR r2,[r0,#0]
;;;149
;;;150 /* Reset HSEBYP bit */
;;;151 RCC->CR &= 0xFFFBFFFF;
00002c 6802 LDR r2,[r0,#0]
00002e f422f422 BIC r2,r2,#0x40000
000032 6002 STR r2,[r0,#0]
;;;152
;;;153 /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
;;;154 RCC->CFGR &= 0xFF80FFFF;
000034 6842 LDR r2,[r0,#4]
000036 f422f422 BIC r2,r2,#0x7f0000
00003a 6042 STR r2,[r0,#4]
;;;155
;;;156 /* Disable all interrupts */
;;;157 RCC->CIR = 0x00000000;
00003c 6081 STR r1,[r0,#8]
;;;158 }
00003e 4770 BX lr
;;;159
ENDP
RCC_HSEConfig PROC
;;;180 /* Reset HSEON bit */
;;;181 RCC->CR &= CR_HSEON_Reset;
000040 49a8 LDR r1,|L1.740|
000042 680a LDR r2,[r1,#0]
000044 f422f422 BIC r2,r2,#0x10000
000048 600a STR r2,[r1,#0]
;;;182
;;;183 /* Reset HSEBYP bit */
;;;184 RCC->CR &= CR_HSEBYP_Reset;
00004a 680a LDR r2,[r1,#0]
00004c f422f422 BIC r2,r2,#0x40000
000050 600a STR r2,[r1,#0]
;;;185
;;;186 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
;;;187 switch(RCC_HSE)
000052 f5b0f5b0 CMP r0,#0x10000
000056 d007 BEQ |L1.104|
000058 f5b0f5b0 CMP r0,#0x40000
00005c d103 BNE |L1.102|
;;;188 {
;;;189 case RCC_HSE_ON:
;;;190 /* Set HSEON bit */
;;;191 RCC->CR |= CR_HSEON_Set;
;;;192 break;
;;;193
;;;194 case RCC_HSE_Bypass:
;;;195 /* Set HSEBYP and HSEON bits */
;;;196 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
00005e 6808 LDR r0,[r1,#0]
000060 f440f440 ORR r0,r0,#0x50000
000064 6008 STR r0,[r1,#0]
|L1.102|
;;;197 break;
;;;198
;;;199 default:
;;;200 break;
;;;201 }
;;;202 }
000066 4770 BX lr
|L1.104|
000068 6808 LDR r0,[r1,#0]
00006a f440f440 ORR r0,r0,#0x10000
00006e 6008 STR r0,[r1,#0]
000070 4770 BX lr
;;;203
ENDP
RCC_GetFlagStatus PROC
;;;990 u32 statusreg = 0;
;;;991 FlagStatus bitstatus = RESET;
000072 2200 MOVS r2,#0
;;;992
;;;993 /* Check the parameters */
;;;994 assert(IS_RCC_FLAG(RCC_FLAG));
;;;995
;;;996 /* Get the RCC register index */
;;;997 tmp = RCC_FLAG >> 5;
000074 0941 LSRS r1,r0,#5
;;;998
;;;999 if (tmp == 1) /* The flag to check is in CR register */
000076 4b9b LDR r3,|L1.740|
000078 2901 CMP r1,#1
00007a d101 BNE |L1.128|
;;;1000 {
;;;1001 statusreg = RCC->CR;
00007c 6819 LDR r1,[r3,#0]
00007e e004 B |L1.138|
|L1.128|
;;;1002 }
;;;1003 else if (tmp == 2) /* The flag to check is in BDCR register */
000080 2902 CMP r1,#2
000082 d101 BNE |L1.136|
;;;1004 {
;;;1005 statusreg = RCC->BDCR;
000084 6a19 LDR r1,[r3,#0x20]
000086 e000 B |L1.138|
|L1.136|
;;;1006 }
;;;1007 else /* The flag to check is in CSR register */
;;;1008 {
;;;1009 statusreg = RCC->CSR;
000088 6a59 LDR r1,[r3,#0x24]
|L1.138|
;;;1010 }
;;;1011
;;;1012 /* Get the flag position */
;;;1013 tmp = RCC_FLAG & FLAG_Mask;
00008a f000f000 AND r0,r0,#0x1f
;;;1014
;;;1015 if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
00008e 2301 MOVS r3,#1
000090 fa03fa03 LSL r0,r3,r0
000094 4208 TST r0,r1
000096 d000 BEQ |L1.154|
;;;1016 {
;;;1017 bitstatus = SET;
000098 2201 MOVS r2,#1
|L1.154|
;;;1018 }
;;;1019 else
;;;1020 {
;;;1021 bitstatus = RESET;
;;;1022 }
;;;1023
;;;1024 /* Return the flag status */
;;;1025 return bitstatus;
00009a 4610 MOV r0,r2
;;;1026 }
00009c 4770 BX lr
;;;1027
ENDP
RCC_WaitForHSEStartUp PROC
;;;213 ErrorStatus RCC_WaitForHSEStartUp(void)
;;;214 {
00009e b510 PUSH {r4,lr}
;;;215 vu32 StartUpCounter = 0;
0000a0 2400 MOVS r4,#0
;;;216
;;;217 /* Wait till HSE is ready and if Time out is reached exit */
;;;218 while((RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET) &&
0000a2 e000 B |L1.166|
|L1.164|
;;;219 (StartUpCounter != HSEStartUp_TimeOut))
;;;220 {
;;;221 StartUpCounter++;
0000a4 1c64 ADDS r4,r4,#1
|L1.166|
0000a6 2031 MOVS r0,#0x31
0000a8 f7fff7ff BL RCC_GetFlagStatus
0000ac b908 CBNZ r0,|L1.178|
0000ae 2c80 CMP r4,#0x80
0000b0 d1f8 BNE |L1.164|
|L1.178|
;;;222 }
;;;223
;;;224 if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
0000b2 2031 MOVS r0,#0x31
0000b4 f7fff7ff BL RCC_GetFlagStatus
0000b8 b108 CBZ r0,|L1.190|
;;;225 {
;;;226 return SUCCESS;
0000ba 2001 MOVS r0,#1
;;;227 }
;;;228 else
;;;229 {
;;;230 return ERROR;
;;;231 }
;;;232 }
0000bc bd10 POP {r4,pc}
|L1.190|
0000be 2000 MOVS r0,#0
0000c0 bd10 POP {r4,pc}
;;;233
ENDP
RCC_AdjustHSICalibrationValue PROC
;;;249
;;;250 tmpreg = RCC->CR;
0000c2 4a88 LDR r2,|L1.740|
0000c4 6811 LDR r1,[r2,#0]
;;;251
;;;252 /* Clear HSITRIM[7:3] bits */
;;;253 tmpreg &= CR_HSITRIM_Mask;
0000c6 f021f021 BIC r1,r1,#0xf8
;;;254
;;;255 /* Set the HSITRIM[7:3] bits according to HSICalibrationValue value */
;;;256 tmpreg |= (u32)HSICalibrationValue << 3;
0000ca ea41ea41 ORR r0,r1,r0,LSL #3
;;;257
;;;258 /* Store the new value */
;;;259 RCC->CR = tmpreg;
0000ce 6010 STR r0,[r2,#0]
;;;260 }
0000d0 4770 BX lr
;;;261
ENDP
RCC_HSICmd PROC
;;;276
;;;277 *(vu32 *) CR_HSION_BB = (u32)NewState;
0000d2 4986 LDR r1,|L1.748|
0000d4 6008 STR r0,[r1,#0]
;;;278 }
0000d6 4770 BX lr
;;;279
ENDP
RCC_PLLConfig PROC
;;;304
;;;305 tmpreg = RCC->CFGR;
0000d8 4b82 LDR r3,|L1.740|
0000da 685a LDR r2,[r3,#4]
;;;306
;;;307 /* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */
;;;308 tmpreg &= CFGR_PLL_Mask;
0000dc f422f422 BIC r2,r2,#0x3f0000
;;;309
;;;310 /* Set the PLL configuration bits */
;;;311 tmpreg |= RCC_PLLSource | RCC_PLLMul;
0000e0 4308 ORRS r0,r0,r1
0000e2 4310 ORRS r0,r0,r2
;;;312
;;;313 /* Store the new value */
;;;314 RCC->CFGR = tmpreg;
0000e4 6058 STR r0,[r3,#4]
;;;315 }
0000e6 4770 BX lr
;;;316
ENDP
RCC_PLLCmd PROC
;;;330
;;;331 *(vu32 *) CR_PLLON_BB = (u32)NewState;
0000e8 4980 LDR r1,|L1.748|
0000ea 6608 STR r0,[r1,#0x60]
;;;332 }
0000ec 4770 BX lr
;;;333
ENDP
RCC_SYSCLKConfig PROC
;;;351
;;;352 tmpreg = RCC->CFGR;
0000ee 4a7d LDR r2,|L1.740|
0000f0 6851 LDR r1,[r2,#4]
;;;353
;;;354 /* Clear SW[1:0] bits */
;;;355 tmpreg &= CFGR_SW_Mask;
0000f2 f021f021 BIC r1,r1,#3
;;;356
;;;357 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
;;;358 tmpreg |= RCC_SYSCLKSource;
0000f6 4308 ORRS r0,r0,r1
;;;359
;;;360 /* Store the new value */
;;;361 RCC->CFGR = tmpreg;
0000f8 6050 STR r0,[r2,#4]
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