📄 stm32f10x_spi.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 914] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\rvmdk\stm32f10x_spi.o --depend=.\rvmdk\stm32f10x_spi.d --device=DARMSTM -O1 -Otime -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -I..\..\..\..\..\uC-Probe\Target\Plugins\uCOS-II -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\Source -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Ports\ST\STM32 -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Source -ID:\Keil\ARM\INC\ST\STM32F10x ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_spi.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=1
SPI_DeInit PROC
;;;58 void SPI_DeInit(SPI_TypeDef* SPIx)
;;;59 {
000000 b510 PUSH {r4,lr}
;;;60 switch (*(u32*)&SPIx)
000002 f1a0f1a0 SUB r0,r0,#0x40000000
000006 f5b0f5b0 SUBS r0,r0,#0x3800
00000a d00d BEQ |L1.40|
00000c f5b0f5b0 CMP r0,#0xf800
000010 d115 BNE |L1.62|
;;;61 {
;;;62 case SPI1_BASE:
;;;63 /* Enable SPI1 reset state */
;;;64 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
000012 2101 MOVS r1,#1
000014 0308 LSLS r0,r1,#12
000016 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;65 /* Release SPI1 from reset state */
;;;66 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
00001a e8bde8bd POP {r4,lr}
00001e 2100 MOVS r1,#0
000020 f44ff44f MOV r0,#0x1000
000024 f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.40|
;;;67 break;
;;;68
;;;69 case SPI2_BASE:
;;;70 /* Enable SPI2 reset state */
;;;71 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
000028 2101 MOVS r1,#1
00002a 0388 LSLS r0,r1,#14
00002c f7fff7ff BL RCC_APB1PeriphResetCmd
;;;72 /* Release SPI2 from reset state */
;;;73 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
000030 e8bde8bd POP {r4,lr}
000034 2100 MOVS r1,#0
000036 f44ff44f MOV r0,#0x4000
00003a f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.62|
;;;74 break;
;;;75
;;;76 default:
;;;77 break;
;;;78 }
;;;79 }
00003e bd10 POP {r4,pc}
;;;80
ENDP
SPI_Init PROC
;;;92 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
;;;93 {
000040 b410 PUSH {r4}
;;;94 u16 tmpreg = 0;
;;;95
;;;96 /* Check the parameters */
;;;97 assert(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
;;;98 assert(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
;;;99 assert(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
;;;100 assert(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
;;;101 assert(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
;;;102 assert(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
;;;103 assert(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
;;;104 assert(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
;;;105 assert(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
;;;106
;;;107 /*---------------------------- SPIx CR1 Configuration ------------------------*/
;;;108 /* Get the SPIx CR1 value */
;;;109 tmpreg = SPIx->CR1;
000042 8802 LDRH r2,[r0,#0]
;;;110 /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
;;;111 tmpreg &= CR1_CLEAR_Mask;
000044 f402f402 AND r2,r2,#0x3040
;;;112 /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
;;;113 master/salve mode, CPOL and CPHA */
;;;114 /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
;;;115 /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
;;;116 /* Set LSBFirst bit according to SPI_FirstBit value */
;;;117 /* Set BR bits according to SPI_BaudRatePrescaler value */
;;;118 /* Set CPOL bit according to SPI_CPOL value */
;;;119 /* Set CPHA bit according to SPI_CPHA value */
;;;120 tmpreg |= (u16)((u32)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
000048 880b LDRH r3,[r1,#0]
00004a f8b1f8b1 LDRH r12,[r1,#2]
00004e 88cc LDRH r4,[r1,#6]
000050 ea43ea43 ORR r3,r3,r12
000054 f8b1f8b1 LDRH r12,[r1,#4]
000058 ea4cea4c ORR r12,r12,r4
00005c ea43ea43 ORR r3,r3,r12
000060 f8b1f8b1 LDRH r12,[r1,#8]
000064 ea43ea43 ORR r3,r3,r12
000068 f8b1f8b1 LDRH r12,[r1,#0xa]
00006c ea43ea43 ORR r3,r3,r12
000070 f8b1f8b1 LDRH r12,[r1,#0xc]
000074 ea43ea43 ORR r3,r3,r12
000078 f8b1f8b1 LDRH r12,[r1,#0xe]
00007c ea43ea43 ORR r3,r3,r12
000080 431a ORRS r2,r2,r3
;;;121 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
;;;122 SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
;;;123 SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
;;;124 /* Write to SPIx CR1 */
;;;125 SPIx->CR1 = tmpreg;
000082 8002 STRH r2,[r0,#0]
;;;126
;;;127 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
;;;128 /* Write to SPIx CRCPOLY */
;;;129 SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
000084 8a09 LDRH r1,[r1,#0x10]
000086 8201 STRH r1,[r0,#0x10]
;;;130 }
000088 bc10 POP {r4}
00008a 4770 BX lr
;;;131
ENDP
SPI_StructInit PROC
;;;143 /* Initialize the SPI_Direction member */
;;;144 SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00008c 2100 MOVS r1,#0
00008e 8001 STRH r1,[r0,#0]
;;;145
;;;146 /* initialize the SPI_Mode member */
;;;147 SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
000090 8041 STRH r1,[r0,#2]
;;;148
;;;149 /* initialize the SPI_DataSize member */
;;;150 SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
000092 8081 STRH r1,[r0,#4]
;;;151
;;;152 /* Initialize the SPI_CPOL member */
;;;153 SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
000094 80c1 STRH r1,[r0,#6]
;;;154
;;;155 /* Initialize the SPI_CPHA member */
;;;156 SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
000096 8101 STRH r1,[r0,#8]
;;;157
;;;158 /* Initialize the SPI_NSS member */
;;;159 SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
000098 8141 STRH r1,[r0,#0xa]
;;;160
;;;161 /* Initialize the SPI_BaudRatePrescaler member */
;;;162 SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
00009a 8181 STRH r1,[r0,#0xc]
;;;163
;;;164 /* Initialize the SPI_FirstBit member */
;;;165 SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
00009c 81c1 STRH r1,[r0,#0xe]
;;;166
;;;167 /* Initialize the SPI_CRCPolynomial member */
;;;168 SPI_InitStruct->SPI_CRCPolynomial = 7;
00009e 2107 MOVS r1,#7
0000a0 8201 STRH r1,[r0,#0x10]
;;;169 }
0000a2 4770 BX lr
;;;170
ENDP
SPI_Cmd PROC
;;;184
;;;185 if (NewState != DISABLE)
0000a4 b121 CBZ r1,|L1.176|
;;;186 {
;;;187 /* Enable the selected SPI peripheral */
;;;188 SPIx->CR1 |= CR1_SPE_Set;
0000a6 8801 LDRH r1,[r0,#0]
0000a8 f041f041 ORR r1,r1,#0x40
0000ac 8001 STRH r1,[r0,#0]
;;;189 }
;;;190 else
;;;191 {
;;;192 /* Disable the selected SPI peripheral */
;;;193 SPIx->CR1 &= CR1_SPE_Reset;
;;;194 }
;;;195 }
0000ae 4770 BX lr
|L1.176|
0000b0 8801 LDRH r1,[r0,#0]
0000b2 f021f021 BIC r1,r1,#0x40
0000b6 8001 STRH r1,[r0,#0]
0000b8 4770 BX lr
;;;196
ENDP
SPI_ITConfig PROC
;;;220 /* Get the SPI IT index */
;;;221 itpos = SPI_IT >> 4;
0000ba 0909 LSRS r1,r1,#4
;;;222 /* Set the IT mask */
;;;223 itmask = (u16)((u16)1 << itpos);
0000bc 2301 MOVS r3,#1
0000be fa03fa03 LSL r1,r3,r1
0000c2 b289 UXTH r1,r1
;;;224
;;;225 if (NewState != DISABLE)
0000c4 b11a CBZ r2,|L1.206|
;;;226 {
;;;227 /* Enable the selected SPI interrupt */
;;;228 SPIx->CR2 |= itmask;
0000c6 8882 LDRH r2,[r0,#4]
0000c8 4311 ORRS r1,r1,r2
0000ca 8081 STRH r1,[r0,#4]
;;;229 }
;;;230 else
;;;231 {
;;;232 /* Disable the selected SPI interrupt */
;;;233 SPIx->CR2 &= (u16)~itmask;
;;;234 }
;;;235 }
0000cc 4770 BX lr
|L1.206|
0000ce 8882 LDRH r2,[r0,#4]
0000d0 ea22ea22 BIC r1,r2,r1
0000d4 8081 STRH r1,[r0,#4]
0000d6 4770 BX lr
;;;236
ENDP
SPI_DMACmd PROC
;;;256
;;;257 if (NewState != DISABLE)
0000d8 b11a CBZ r2,|L1.226|
;;;258 {
;;;259 /* Enable the selected SPI DMA requests */
;;;260 SPIx->CR2 |= SPI_DMAReq;
0000da 8882 LDRH r2,[r0,#4]
0000dc 4311 ORRS r1,r1,r2
0000de 8081 STRH r1,[r0,#4]
;;;261 }
;;;262 else
;;;263 {
;;;264 /* Disable the selected SPI DMA requests */
;;;265 SPIx->CR2 &= (u16)~SPI_DMAReq;
;;;266 }
;;;267 }
0000e0 4770 BX lr
|L1.226|
0000e2 8882 LDRH r2,[r0,#4]
0000e4 ea22ea22 BIC r1,r2,r1
0000e8 8081 STRH r1,[r0,#4]
0000ea 4770 BX lr
;;;268
ENDP
SPI_SendData PROC
;;;279 /* Write in the DR register the data to be sent */
;;;280 SPIx->DR = Data;
0000ec 8181 STRH r1,[r0,#0xc]
;;;281 }
0000ee 4770 BX lr
;;;282
ENDP
SPI_ReceiveData PROC
;;;292 /* Return the data in the DR register */
;;;293 return SPIx->DR;
0000f0 8980 LDRH r0,[r0,#0xc]
;;;294 }
0000f2 4770 BX lr
;;;295
ENDP
SPI_NSSInternalSoftwareConfig PROC
;;;312
;;;313 if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
0000f4 f5a1f5a1 SUB r2,r1,#0xfe00
0000f8 3aff SUBS r2,r2,#0xff
0000fa d004 BEQ |L1.262|
;;;314 {
;;;315 /* Set NSS pin internally by software */
;;;316 SPIx->CR1 |= SPI_NSSInternalSoft_Set;
0000fc 8801 LDRH r1,[r0,#0]
0000fe f441f441 ORR r1,r1,#0x100
000102 8001 STRH r1,[r0,#0]
;;;317 }
;;;318 else
;;;319 {
;;;320 /* Reset NSS pin internally by software */
;;;321 SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
;;;322 }
;;;323 }
000104 4770 BX lr
|L1.262|
000106 8801 LDRH r1,[r0,#0]
000108 f421f421 BIC r1,r1,#0x100
00010c 8001 STRH r1,[r0,#0]
00010e 4770 BX lr
;;;324
ENDP
SPI_SSOutputCmd PROC
;;;338
;;;339 if (NewState != DISABLE)
000110 b121 CBZ r1,|L1.284|
;;;340 {
;;;341 /* Enable the selected SPI SS output */
;;;342 SPIx->CR2 |= CR2_SSOE_Set;
000112 8881 LDRH r1,[r0,#4]
000114 f041f041 ORR r1,r1,#4
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