stm32f10x_pwr.txt

ucos2.86版本结合STM板极支持包

; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 914] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\rvmdk\stm32f10x_pwr.o --depend=.\rvmdk\stm32f10x_pwr.d --device=DARMSTM -O1 -Otime -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -I..\..\..\..\..\uC-Probe\Target\Plugins\uCOS-II -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\Source -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Ports\ST\STM32 -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Source -ID:\Keil\ARM\INC\ST\STM32F10x ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_pwr.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  PWR_DeInit PROC
;;;72     void PWR_DeInit(void)
;;;73     {
000000  b510              PUSH     {r4,lr}
;;;74       RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
000002  2101              MOVS     r1,#1
000004  0708              LSLS     r0,r1,#28
000006  f7fff7ff          BL       RCC_APB1PeriphResetCmd
;;;75       RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
00000a  e8bde8bd          POP      {r4,lr}
00000e  2100              MOVS     r1,#0
000010  f04ff04f          MOV      r0,#0x10000000
000014  f7fff7ff          B.W      RCC_APB1PeriphResetCmd
;;;76     }
;;;77     
                          ENDP

                  PWR_BackupAccessCmd PROC
;;;90     
;;;91       *(vu32 *) CR_DBP_BB = (u32)NewState;
000018  491f              LDR      r1,|L1.152|
00001a  6208              STR      r0,[r1,#0x20]
;;;92     }
00001c  4770              BX       lr
;;;93     
                          ENDP

                  PWR_PVDCmd PROC
;;;106    
;;;107      *(vu32 *) CR_PVDE_BB = (u32)NewState;
00001e  491e              LDR      r1,|L1.152|
000020  6108              STR      r0,[r1,#0x10]
;;;108    }
000022  4770              BX       lr
;;;109    
                          ENDP

                  PWR_PVDLevelConfig PROC
;;;133    
;;;134      tmpreg = PWR->CR;
000024  4a1d              LDR      r2,|L1.156|
000026  6811              LDR      r1,[r2,#0]
;;;135    
;;;136      /* Clear PLS[7:5] bits */
;;;137      tmpreg &= CR_PLS_Mask;
000028  f021f021          BIC      r1,r1,#0xe0
;;;138    
;;;139      /* Set PLS[7:5] bits according to PWR_PVDLevel value */
;;;140      tmpreg |= PWR_PVDLevel;
00002c  4308              ORRS     r0,r0,r1
;;;141    
;;;142      /* Store the new value */
;;;143      PWR->CR = tmpreg;
00002e  6010              STR      r0,[r2,#0]
;;;144    }
000030  4770              BX       lr
;;;145    
                          ENDP

                  PWR_WakeUpPinCmd PROC
;;;158    
;;;159      *(vu32 *) CSR_EWUP_BB = (u32)NewState;
000032  491b              LDR      r1,|L1.160|
000034  6008              STR      r0,[r1,#0]
;;;160    }
000036  4770              BX       lr
;;;161    
                          ENDP

                  PWR_EnterSTOPMode PROC
;;;186      /* Select the regulator state in STOP mode ---------------------------------*/
;;;187      tmpreg = PWR->CR;
000038  4b18              LDR      r3,|L1.156|
00003a  681a              LDR      r2,[r3,#0]
;;;188    
;;;189      /* Clear PDDS and LPDS bits */
;;;190      tmpreg &= CR_DS_Mask;
00003c  f022f022          BIC      r2,r2,#3
;;;191    
;;;192      /* Set LPDS bit according to PWR_Regulator value */
;;;193      tmpreg |= PWR_Regulator;
000040  4310              ORRS     r0,r0,r2
;;;194    
;;;195      /* Store the new value */
;;;196      PWR->CR = tmpreg;
000042  6018              STR      r0,[r3,#0]
;;;197    
;;;198      /* Set SLEEPDEEP bit of Cortex System Control Register */
;;;199      *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
000044  4817              LDR      r0,|L1.164|
000046  6802              LDR      r2,[r0,#0]
000048  f042f042          ORR      r2,r2,#4
00004c  6002              STR      r2,[r0,#0]
;;;200      
;;;201      /* Select STOP mode entry --------------------------------------------------*/
;;;202      if(PWR_STOPEntry == PWR_STOPEntry_WFI)
00004e  2901              CMP      r1,#1
000050  d101              BNE      |L1.86|
;;;203      {   
;;;204        /* Request Wait For Interrupt */
;;;205        __WFI();
000052  f7fff7ff          B.W      __WFI
                  |L1.86|
;;;206      }
;;;207      else
;;;208      {
;;;209        /* Request Wait For Event */
;;;210        __WFE();
000056  f7fff7ff          B.W      __WFE
;;;211      }
;;;212    }
;;;213    
                          ENDP

                  PWR_EnterSTANDBYMode PROC
;;;223      /* Clear Wake-up flag */
;;;224      PWR->CR |= CR_CWUF_Set;
00005a  4810              LDR      r0,|L1.156|
00005c  6801              LDR      r1,[r0,#0]
00005e  f041f041          ORR      r1,r1,#4
000062  6001              STR      r1,[r0,#0]
;;;225    
;;;226      /* Select STANDBY mode */
;;;227      PWR->CR |= CR_PDDS_Set;
000064  6801              LDR      r1,[r0,#0]
000066  f041f041          ORR      r1,r1,#2
00006a  6001              STR      r1,[r0,#0]
;;;228    
;;;229      /* Set SLEEPDEEP bit of Cortex System Control Register */
;;;230      *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
00006c  480d              LDR      r0,|L1.164|
00006e  6801              LDR      r1,[r0,#0]
000070  f041f041          ORR      r1,r1,#4
000074  6001              STR      r1,[r0,#0]
;;;231    
;;;232      /* Request Wait For Interrupt */
;;;233      __WFI();
000076  f7fff7ff          B.W      __WFI
;;;234    }
;;;235    
                          ENDP

                  PWR_GetFlagStatus PROC
;;;247    FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG)
;;;248    {
00007a  4601              MOV      r1,r0
;;;249      FlagStatus bitstatus = RESET;
00007c  2000              MOVS     r0,#0
;;;250    
;;;251      /* Check the parameters */
;;;252      assert(IS_PWR_GET_FLAG(PWR_FLAG));
;;;253      
;;;254      if ((PWR->CSR & PWR_FLAG) != (u32)RESET)
00007e  4a07              LDR      r2,|L1.156|
000080  6852              LDR      r2,[r2,#4]
000082  420a              TST      r2,r1
000084  d000              BEQ      |L1.136|
;;;255      {
;;;256        bitstatus = SET;
000086  2001              MOVS     r0,#1
                  |L1.136|
;;;257      }
;;;258      else
;;;259      {
;;;260        bitstatus = RESET;
;;;261      }
;;;262    
;;;263      /* Return the flag status */
;;;264      return bitstatus;
;;;265    }
000088  4770              BX       lr
;;;266    
                          ENDP

                  PWR_ClearFlag PROC
;;;281             
;;;282      PWR->CR |=  PWR_FLAG << 2;
00008a  4904              LDR      r1,|L1.156|
00008c  680a              LDR      r2,[r1,#0]
00008e  ea42ea42          ORR      r0,r2,r0,LSL #2
000092  6008              STR      r0,[r1,#0]
;;;283    }
000094  4770              BX       lr
;;;284    
                          ENDP

000096  0000              DCW      0x0000
                  |L1.152|
000098  420e0000          DCD      0x420e0000
                  |L1.156|
00009c  40007000          DCD      0x40007000
                  |L1.160|
0000a0  420e00a0          DCD      0x420e00a0
                  |L1.164|
0000a4  e000ed10          DCD      0xe000ed10