stm32f10x_bkp.txt

ucos2.86版本结合STM板极支持包

; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 914] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\rvmdk\stm32f10x_bkp.o --depend=.\rvmdk\stm32f10x_bkp.d --device=DARMSTM -O1 -Otime -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -I..\..\..\..\..\uC-Probe\Target\Plugins\uCOS-II -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\Source -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Ports\ST\STM32 -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Source -ID:\Keil\ARM\INC\ST\STM32F10x ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_bkp.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  BKP_DeInit PROC
;;;82     void BKP_DeInit(void)
;;;83     {
000000  b510              PUSH     {r4,lr}
;;;84       RCC_BackupResetCmd(ENABLE);
000002  2001              MOVS     r0,#1
000004  f7fff7ff          BL       RCC_BackupResetCmd
;;;85       RCC_BackupResetCmd(DISABLE);
000008  e8bde8bd          POP      {r4,lr}
00000c  2000              MOVS     r0,#0
00000e  f7fff7ff          B.W      RCC_BackupResetCmd
;;;86     }
;;;87     
                          ENDP

                  BKP_TamperPinLevelConfig PROC
;;;102    
;;;103      *(vu32 *) CR_TPAL_BB = BKP_TamperPinLevel;
000012  491a              LDR      r1,|L1.124|
000014  6008              STR      r0,[r1,#0]
;;;104    }
000016  4770              BX       lr
;;;105    
                          ENDP

                  BKP_TamperPinCmd PROC
;;;118    
;;;119      *(vu32 *) CR_TPE_BB = (u32)NewState;
000018  4919              LDR      r1,|L1.128|
00001a  6008              STR      r0,[r1,#0]
;;;120    }
00001c  4770              BX       lr
;;;121    
                          ENDP

                  BKP_ITConfig PROC
;;;134    
;;;135      *(vu32 *) CSR_TPIE_BB = (u32)NewState;
00001e  4919              LDR      r1,|L1.132|
000020  6008              STR      r0,[r1,#0]
;;;136    }
000022  4770              BX       lr
;;;137    
                          ENDP

                  BKP_RTCCalibrationClockOutputCmd PROC
;;;150    
;;;151      *(vu32 *) RTCCR_CCO_BB = (u32)NewState;
000024  4918              LDR      r1,|L1.136|
000026  6008              STR      r0,[r1,#0]
;;;152    }
000028  4770              BX       lr
;;;153    
                          ENDP

                  BKP_SetRTCCalibrationValue PROC
;;;168    
;;;169      tmpreg = BKP->RTCCR;
00002a  4a18              LDR      r2,|L1.140|
00002c  8811              LDRH     r1,[r2,#0]
;;;170    
;;;171      /* Clear CAL[6:0] bits */
;;;172      tmpreg &= RTCCR_CAL_Mask;
00002e  f021f021          BIC      r1,r1,#0x7f
;;;173    
;;;174      /* Set CAL[6:0] bits according to CalibrationValue value */
;;;175      tmpreg |= CalibrationValue;
000032  4308              ORRS     r0,r0,r1
;;;176    
;;;177      /* Store the new value */
;;;178      BKP->RTCCR = tmpreg;
000034  8010              STRH     r0,[r2,#0]
;;;179    }
000036  4770              BX       lr
;;;180    
                          ENDP

                  BKP_WriteBackupRegister PROC
;;;194    
;;;195      *(vu16 *) (BKP_BASE + BKP_DR) = Data;
000038  f100f100          ADD      r0,r0,#0x40000000
00003c  f500f500          ADD      r0,r0,#0x6000
000040  f8a0f8a0          STRH     r1,[r0,#0xc00]
;;;196    }
000044  4770              BX       lr
;;;197    
                          ENDP

                  BKP_ReadBackupRegister PROC
;;;210    
;;;211      return (*(vu16 *) (BKP_BASE + BKP_DR));
000046  f100f100          ADD      r0,r0,#0x40000000
00004a  f500f500          ADD      r0,r0,#0x6000
00004e  f8b0f8b0          LDRH     r0,[r0,#0xc00]
;;;212    }
000052  4770              BX       lr
;;;213    
                          ENDP

                  BKP_GetFlagStatus PROC
;;;222    {
;;;223      return (FlagStatus)(*(vu32 *) CSR_TEF_BB);
000054  480e              LDR      r0,|L1.144|
000056  6800              LDR      r0,[r0,#0]
000058  b2c0              UXTB     r0,r0
;;;224    }
00005a  4770              BX       lr
;;;225    
                          ENDP

                  BKP_ClearFlag PROC
;;;235      /* Set CTE bit to clear Tamper Pin Event flag */
;;;236      BKP->CSR |= CSR_CTE_Set;
00005c  480d              LDR      r0,|L1.148|
00005e  8801              LDRH     r1,[r0,#0]
000060  f041f041          ORR      r1,r1,#1
000064  8001              STRH     r1,[r0,#0]
;;;237    }
000066  4770              BX       lr
;;;238    
                          ENDP

                  BKP_GetITStatus PROC
;;;247    {
;;;248      return (ITStatus)(*(vu32 *) CSR_TIF_BB);
000068  480b              LDR      r0,|L1.152|
00006a  6800              LDR      r0,[r0,#0]
00006c  b2c0              UXTB     r0,r0
;;;249    }
00006e  4770              BX       lr
;;;250    
                          ENDP

                  BKP_ClearITPendingBit PROC
;;;260      /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
;;;261      BKP->CSR |= CSR_CTI_Set;
000070  4808              LDR      r0,|L1.148|
000072  8801              LDRH     r1,[r0,#0]
000074  f041f041          ORR      r1,r1,#2
000078  8001              STRH     r1,[r0,#0]
;;;262    }
00007a  4770              BX       lr
;;;263    
                          ENDP

                  |L1.124|
00007c  420d8604          DCD      0x420d8604
                  |L1.128|
000080  420d8600          DCD      0x420d8600
                  |L1.132|
000084  420d8688          DCD      0x420d8688
                  |L1.136|
000088  420d859c          DCD      0x420d859c
                  |L1.140|
00008c  40006c2c          DCD      0x40006c2c
                  |L1.144|
000090  420d86a0          DCD      0x420d86a0
                  |L1.148|
000094  40006c34          DCD      0x40006c34
                  |L1.152|
000098  420d86a4          DCD      0x420d86a4