stm32f10x_tim1.txt

ucos2.86版本结合STM板极支持包

0004ee  8811              LDRH     r1,[r2,#0]
;;;1405   
;;;1406     /* Reset the CMS and DIR Bits */
;;;1407     tmpcr1 &= CR1_CounterMode_Mask;
0004f0  f240f240          MOV      r3,#0x39f
0004f4  4019              ANDS     r1,r1,r3
;;;1408   
;;;1409     /* Set the Counter Mode */
;;;1410     tmpcr1 |= TIM1_CounterMode;
0004f6  4308              ORRS     r0,r0,r1
;;;1411   
;;;1412     TIM1->CR1 = (u16)tmpcr1;
0004f8  8010              STRH     r0,[r2,#0]
;;;1413   }
0004fa  4770              BX       lr
;;;1414   
                          ENDP

                  TIM1_ForcedOC1Config PROC
;;;1434   
;;;1435     tmpccmr1 = TIM1->CCMR1;
0004fc  4a94              LDR      r2,|L1.1872|
0004fe  8811              LDRH     r1,[r2,#0]
;;;1436   
;;;1437     /* Reset the OCM Bits */
;;;1438     tmpccmr1 &= CCMR_OCM13_Mask;
000500  f647f647          MOV      r3,#0x7f0f
000504  4019              ANDS     r1,r1,r3
;;;1439   
;;;1440     /* Configure The Forced output Mode */
;;;1441     tmpccmr1 |= TIM1_ForcedAction;
000506  4308              ORRS     r0,r0,r1
;;;1442   
;;;1443     TIM1->CCMR1 = (u16)tmpccmr1;
000508  8010              STRH     r0,[r2,#0]
;;;1444   }
00050a  4770              BX       lr
;;;1445   
                          ENDP

                  TIM1_ForcedOC2Config PROC
;;;1465   
;;;1466     tmpccmr1 = TIM1->CCMR1;
00050c  4a90              LDR      r2,|L1.1872|
00050e  8811              LDRH     r1,[r2,#0]
;;;1467   
;;;1468     /* Reset the OCM Bits */
;;;1469     tmpccmr1 &= CCMR_OCM24_Mask;
000510  f640f640          MOV      r3,#0xf7f
000514  4019              ANDS     r1,r1,r3
;;;1470   
;;;1471     /* Configure The Forced output Mode */
;;;1472     tmpccmr1 |= (u32)TIM1_ForcedAction << 8;
000516  ea41ea41          ORR      r0,r1,r0,LSL #8
;;;1473   
;;;1474     TIM1->CCMR1 = (u16)tmpccmr1;
00051a  8010              STRH     r0,[r2,#0]
;;;1475   }
00051c  4770              BX       lr
;;;1476   
                          ENDP

                  TIM1_ForcedOC3Config PROC
;;;1496   
;;;1497     tmpccmr2 = TIM1->CCMR2;
00051e  4a8d              LDR      r2,|L1.1876|
000520  8811              LDRH     r1,[r2,#0]
;;;1498   
;;;1499     /* Reset the OCM Bits */
;;;1500     tmpccmr2 &= CCMR_OCM13_Mask;
000522  f647f647          MOV      r3,#0x7f0f
000526  4019              ANDS     r1,r1,r3
;;;1501   
;;;1502     /* Configure The Forced output Mode */
;;;1503     tmpccmr2 |= TIM1_ForcedAction;
000528  4308              ORRS     r0,r0,r1
;;;1504   
;;;1505     TIM1->CCMR2 = (u16)tmpccmr2;
00052a  8010              STRH     r0,[r2,#0]
;;;1506   }
00052c  4770              BX       lr
;;;1507   
                          ENDP

                  TIM1_ForcedOC4Config PROC
;;;1527   
;;;1528     tmpccmr2 = TIM1->CCMR1;
00052e  4a88              LDR      r2,|L1.1872|
000530  8811              LDRH     r1,[r2,#0]
;;;1529   
;;;1530     /* Reset the OCM Bits */
;;;1531     tmpccmr2 &= CCMR_OCM24_Mask;
000532  f640f640          MOV      r3,#0xf7f
000536  4019              ANDS     r1,r1,r3
;;;1532   
;;;1533     /* Configure The Forced output Mode */
;;;1534     tmpccmr2 |= (u16)((u16)TIM1_ForcedAction << 8);
000538  ea41ea41          ORR      r0,r1,r0,LSL #8
;;;1535   
;;;1536     TIM1->CCMR2 = (u16)tmpccmr2;
00053c  8090              STRH     r0,[r2,#4]
;;;1537   }
00053e  4770              BX       lr
;;;1538   
                          ENDP

                  TIM1_ARRPreloadConfig PROC
;;;1552     /* Set or Reset the ARPE Bit */
;;;1553     *(vu32 *) CR1_ARPE_BB = (u16)Newstate;
000540  497c              LDR      r1,|L1.1844|
000542  61c8              STR      r0,[r1,#0x1c]
;;;1554   }
000544  4770              BX       lr
;;;1555   
                          ENDP

                  TIM1_SelectCOM PROC
;;;1569     /* Set or Reset the CCUS Bit */
;;;1570     *(vu32 *) CR2_CCUS_BB = (u16)Newstate;
000546  4984              LDR      r1,|L1.1880|
000548  6008              STR      r0,[r1,#0]
;;;1571   }
00054a  4770              BX       lr
;;;1572   
                          ENDP

                  TIM1_SelectCCDMA PROC
;;;1586     /* Set or Reset the CCDS Bit */
;;;1587     *(vu32 *) CR2_CCDS_BB = (u16)Newstate;
00054c  4983              LDR      r1,|L1.1884|
00054e  6008              STR      r0,[r1,#0]
;;;1588   }
000550  4770              BX       lr
;;;1589   
                          ENDP

                  TIM1_CCPreloadControl PROC
;;;1604     /* Set or Reset the CCPC Bit */
;;;1605     *(vu32 *) CR2_CCPC_BB = (u16)Newstate;
000552  4983              LDR      r1,|L1.1888|
000554  6008              STR      r0,[r1,#0]
;;;1606   }
000556  4770              BX       lr
;;;1607   
                          ENDP

                  TIM1_OC1PreloadConfig PROC
;;;1624     /* Set or Reset the OC1PE Bit */
;;;1625     *(vu32 *) CCMR1_OC1PE_BB = (u16)TIM1_OCPreload;
000558  4982              LDR      r1,|L1.1892|
00055a  6008              STR      r0,[r1,#0]
;;;1626   }
00055c  4770              BX       lr
;;;1627   
                          ENDP

                  TIM1_OC2PreloadConfig PROC
;;;1644     /* Set or Reset the OC2PE Bit */
;;;1645     *(vu32 *) CCMR1_OC2PE_BB = (u16)TIM1_OCPreload;
00055e  4982              LDR      r1,|L1.1896|
000560  6008              STR      r0,[r1,#0]
;;;1646   }
000562  4770              BX       lr
;;;1647   
                          ENDP

                  TIM1_OC3PreloadConfig PROC
;;;1664     /* Set or Reset the OC3PE Bit */
;;;1665     *(vu32 *) CCMR2_OC3PE_BB = (u16)TIM1_OCPreload;
000564  4981              LDR      r1,|L1.1900|
000566  6008              STR      r0,[r1,#0]
;;;1666   }
000568  4770              BX       lr
;;;1667   
                          ENDP

                  TIM1_OC4PreloadConfig PROC
;;;1684     /* Set or Reset the OC4PE Bit */
;;;1685     *(vu32 *) CCMR2_OC4PE_BB = (u16)TIM1_OCPreload;
00056a  4981              LDR      r1,|L1.1904|
00056c  6008              STR      r0,[r1,#0]
;;;1686   }
00056e  4770              BX       lr
;;;1687   
                          ENDP

                  TIM1_OC1FastConfig PROC
;;;1703     /* Set or Reset the OC1FE Bit */
;;;1704     *(vu32 *) CCMR1_OC1FE_BB = (u16)TIM1_OCFast;
000570  4980              LDR      r1,|L1.1908|
000572  6008              STR      r0,[r1,#0]
;;;1705   }
000574  4770              BX       lr
;;;1706   
                          ENDP

                  TIM1_OC2FastConfig PROC
;;;1722     /* Set or Reset the OC2FE Bit */
;;;1723     *(vu32 *) CCMR1_OC2FE_BB = (u16)TIM1_OCFast;
000576  4980              LDR      r1,|L1.1912|
000578  6008              STR      r0,[r1,#0]
;;;1724   }
00057a  4770              BX       lr
;;;1725   
                          ENDP

                  TIM1_OC3FastConfig PROC
;;;1741     /* Set or Reset the OC3FE Bit */
;;;1742     *(vu32 *) CCMR2_OC3FE_BB = (u16)TIM1_OCFast;
00057c  497f              LDR      r1,|L1.1916|
00057e  6008              STR      r0,[r1,#0]
;;;1743   }
000580  4770              BX       lr
;;;1744   
                          ENDP

                  TIM1_OC4FastConfig PROC
;;;1760     /* Set or Reset the OC4FE Bit */
;;;1761     *(vu32 *) CCMR2_OC4FE_BB = (u16)TIM1_OCFast;
000582  497f              LDR      r1,|L1.1920|
000584  6008              STR      r0,[r1,#0]
;;;1762   }
000586  4770              BX       lr
;;;1763   
                          ENDP

                  TIM1_ClearOC1Ref PROC
;;;1779     /* Set or Reset the OC1CE Bit */
;;;1780     *(vu32 *) CCMR1_OC1CE_BB = (u16)TIM1_OCClear;
000588  497e              LDR      r1,|L1.1924|
00058a  6008              STR      r0,[r1,#0]
;;;1781   }
00058c  4770              BX       lr
;;;1782   
                          ENDP

                  TIM1_ClearOC2Ref PROC
;;;1798     /* Set or Reset the OC2CE Bit */
;;;1799     *(vu32 *) CCMR1_OC2CE_BB = (u16)TIM1_OCClear;
00058e  497e              LDR      r1,|L1.1928|
000590  6008              STR      r0,[r1,#0]
;;;1800   }
000592  4770              BX       lr
;;;1801   
                          ENDP

                  TIM1_ClearOC3Ref PROC
;;;1817     /* Set or Reset the OC3CE Bit */
;;;1818     *(vu32 *) CCMR2_OC3CE_BB = (u16)TIM1_OCClear;
000594  497d              LDR      r1,|L1.1932|
000596  6008              STR      r0,[r1,#0]
;;;1819   }
000598  4770              BX       lr
;;;1820   
                          ENDP

                  TIM1_ClearOC4Ref PROC
;;;1836     /* Set or Reset the OC4CE Bit */
;;;1837     *(vu32 *) CCMR2_OC4CE_BB = (u16)TIM1_OCClear;
00059a  497d              LDR      r1,|L1.1936|
00059c  6008              STR      r0,[r1,#0]
;;;1838   }
00059e  4770              BX       lr
;;;1839   
                          ENDP

                  TIM1_GenerateEvent PROC
;;;1861     /* Set the event sources */
;;;1862     TIM1->EGR |= TIM1_EventSource;
0005a0  497c              LDR      r1,|L1.1940|
0005a2  880a              LDRH     r2,[r1,#0]
0005a4  4310              ORRS     r0,r0,r2
0005a6  8008              STRH     r0,[r1,#0]
;;;1863   }
0005a8  4770              BX       lr
;;;1864   
                          ENDP

                  TIM1_OC1PolarityConfig PROC
;;;1880     /* Set or Reset the CC1P Bit */
;;;1881     *(vu32 *) CCER_CC1P_BB = (u16)TIM1_OCPolarity;
0005aa  4966              LDR      r1,|L1.1860|
0005ac  6008              STR      r0,[r1,#0]
;;;1882   }
0005ae  4770              BX       lr
;;;1883   
                          ENDP

                  TIM1_OC1NPolarityConfig PROC
;;;1899     /* Set or Reset the CC3P Bit */
;;;1900     *(vu32 *) CCER_CC1NP_BB = (u16)TIM1_OCPolarity;
0005b0  4979              LDR      r1,|L1.1944|
0005b2  6008              STR      r0,[r1,#0]
;;;1901   }
0005b4  4770              BX       lr
;;;1902   
                          ENDP

                  TIM1_OC2PolarityConfig PROC
;;;1918     /* Set or Reset the CC2P Bit */
;;;1919     *(vu32 *) CCER_CC2P_BB = (u16)TIM1_OCPolarity;
0005b6  4979              LDR      r1,|L1.1948|
0005b8  6008              STR      r0,[r1,#0]
;;;1920   }
0005ba  4770              BX       lr
;;;1921   
                          ENDP

                  TIM1_OC2NPolarityConfig PROC
;;;1937     /* Set or Reset the CC3P Bit */
;;;1938     *(vu32 *) CCER_CC2NP_BB = (u16)TIM1_OCPolarity;
0005bc  4978              LDR      r1,|L1.1952|
0005be  6008              STR      r0,[r1,#0]
;;;1939   }
0005c0  4770              BX       lr
;;;1940   
                          ENDP

                  TIM1_OC3PolarityConfig PROC
;;;1956     /* Set or Reset the CC3P Bit */
;;;1957     *(vu32 *) CCER_CC3P_BB = (u16)TIM1_OCPolarity;
0005c2  4978              LDR      r1,|L1.1956|
0005c4  6008              STR      r0,[r1,#0]
;;;1958   }
0005c6  4770              BX       lr
;;;1959   
                          ENDP

                  TIM1_OC3NPolarityConfig PROC
;;;1975     /* Set or Reset the CC3P Bit */
;;;1976     *(vu32 *) CCER_CC3NP_BB = (u16)TIM1_OCPolarity;
0005c8  4977              LDR      r1,|L1.1960|