📄 stm32f10x_tim1.txt
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;;;981
;;;982 /* Select the External clock mode1 */
;;;983 TIM1->SMCR &= SMCR_SMS_Mask;
0003aa 4825 LDR r0,|L1.1088|
0003ac 8801 LDRH r1,[r0,#0]
0003ae f021f021 BIC r1,r1,#0xf
0003b2 8001 STRH r1,[r0,#0]
;;;984 TIM1->SMCR |= TIM1_SlaveMode_External1;
0003b4 8801 LDRH r1,[r0,#0]
0003b6 f041f041 ORR r1,r1,#7
0003ba 8001 STRH r1,[r0,#0]
;;;985
;;;986 /* Select the Trigger selection : ETRF */
;;;987 TIM1->SMCR &= SMCR_TS_Mask;
0003bc 8801 LDRH r1,[r0,#0]
0003be f021f021 BIC r1,r1,#0x78
0003c2 8001 STRH r1,[r0,#0]
;;;988 TIM1->SMCR |= TIM1_TS_ETRF;
0003c4 8801 LDRH r1,[r0,#0]
0003c6 f041f041 ORR r1,r1,#0x70
0003ca 8001 STRH r1,[r0,#0]
;;;989 }
0003cc bd00 POP {pc}
;;;990
ENDP
TIM1_ETRClockMode2Config PROC
;;;1010 u16 ExtTRGFilter)
;;;1011 {
0003ce b500 PUSH {lr}
;;;1012 /* Check the parameters */
;;;1013 assert(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler));
;;;1014 assert(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity));
;;;1015
;;;1016 /* Configure the ETR Clock source */
;;;1017 TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
0003d0 f7fff7ff BL TIM1_ETRConfig
;;;1018
;;;1019 /* Enable the External clock mode2 */
;;;1020 *(vu32 *) SMCR_ECE_BB = SMCR_ECE_Set;
0003d4 491b LDR r1,|L1.1092|
0003d6 2001 MOVS r0,#1
0003d8 6008 STR r0,[r1,#0]
;;;1021 }
0003da bd00 POP {pc}
;;;1022
ENDP
TIM1_SelectInputTrigger PROC
;;;1142
;;;1143 tmpsmcr = TIM1->SMCR;
0003dc 4a18 LDR r2,|L1.1088|
0003de 8811 LDRH r1,[r2,#0]
;;;1144
;;;1145 /* Select the Tgigger Source */
;;;1146 tmpsmcr &= SMCR_TS_Mask;
0003e0 f64ff64f MOV r3,#0xff87
0003e4 4019 ANDS r1,r1,r3
;;;1147 tmpsmcr |= TIM1_InputTriggerSource;
0003e6 4308 ORRS r0,r0,r1
;;;1148
;;;1149 TIM1->SMCR = (u16)tmpsmcr;
0003e8 8010 STRH r0,[r2,#0]
;;;1150 }
0003ea 4770 BX lr
;;;1151
ENDP
TIM1_ITRxExternalClockConfig PROC
;;;1067 void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource)
;;;1068 {
0003ec b500 PUSH {lr}
;;;1069 /* Check the parameters */
;;;1070 assert(IS_TIM1_INTERNAL_TRIGGER_SELECTION(TIM1_InputTriggerSource));
;;;1071
;;;1072 /* Select the Internal Trigger */
;;;1073 TIM1_SelectInputTrigger(TIM1_InputTriggerSource);
0003ee f7fff7ff BL TIM1_SelectInputTrigger
;;;1074
;;;1075 /* Select the External clock mode1 */
;;;1076 TIM1->SMCR |= TIM1_SlaveMode_External1;
0003f2 4813 LDR r0,|L1.1088|
0003f4 8801 LDRH r1,[r0,#0]
0003f6 f041f041 ORR r1,r1,#7
0003fa 8001 STRH r1,[r0,#0]
;;;1077 }
0003fc bd00 POP {pc}
0003fe 0000 DCW 0x0000
|L1.1024|
000400 40012c00 DCD 0x40012c00
|L1.1028|
000404 40012c18 DCD 0x40012c18
|L1.1032|
000408 422580a0 DCD 0x422580a0
|L1.1036|
00040c 422580a8 DCD 0x422580a8
|L1.1040|
000410 40012c1c DCD 0x40012c1c
|L1.1044|
000414 422580b0 DCD 0x422580b0
|L1.1048|
000418 4225807c DCD 0x4225807c
|L1.1052|
00041c 40012c44 DCD 0x40012c44
|L1.1056|
000420 40012000 DCD 0x40012000
|L1.1060|
000424 42258430 DCD 0x42258430
|L1.1064|
000428 42258420 DCD 0x42258420
|L1.1068|
00042c 42258410 DCD 0x42258410
|L1.1072|
000430 42258400 DCD 0x42258400
|L1.1076|
000434 42258000 DCD 0x42258000
|L1.1080|
000438 422588bc DCD 0x422588bc
|L1.1084|
00043c 40012c48 DCD 0x40012c48
|L1.1088|
000440 40012c08 DCD 0x40012c08
|L1.1092|
000444 42258138 DCD 0x42258138
ENDP
TIM1_TIxExternalClockConfig PROC
;;;1097 u16 TIM1_ICPolarity, u8 ICFilter)
;;;1098 {
000448 b510 PUSH {r4,lr}
00044a 4604 MOV r4,r0
00044c 4608 MOV r0,r1
;;;1099 /* Check the parameters */
;;;1100 assert(IS_TIM1_TIX_TRIGGER_SELECTION(TIM1_TIxExternalCLKSource));
;;;1101 assert(IS_TIM1_IC_POLARITY(TIM1_ICPolarity));
;;;1102 assert(IS_TIM1_IC_FILTER(ICFilter));
;;;1103
;;;1104 /* Configure the TIM1 Input Clock Source */
;;;1105 if (TIM1_TIxExternalCLKSource == TIM1_TIxExternalCLK1Source_TI2)
00044e 2c60 CMP r4,#0x60
000450 d103 BNE |L1.1114|
;;;1106 {
;;;1107 TI2_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter);
000452 2101 MOVS r1,#1
000454 f7fff7ff BL TI2_Config
000458 e002 B |L1.1120|
|L1.1114|
;;;1108 }
;;;1109 else
;;;1110 {
;;;1111 TI1_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter);
00045a 2101 MOVS r1,#1
00045c f7fff7ff BL TI1_Config
|L1.1120|
;;;1112 }
;;;1113
;;;1114 /* Select the Trigger source */
;;;1115 TIM1_SelectInputTrigger(TIM1_TIxExternalCLKSource);
000460 4620 MOV r0,r4
000462 f7fff7ff BL TIM1_SelectInputTrigger
;;;1116
;;;1117 /* Select the External clock mode1 */
;;;1118 TIM1->SMCR |= TIM1_SlaveMode_External1;
000466 48b2 LDR r0,|L1.1840|
000468 8801 LDRH r1,[r0,#0]
00046a f041f041 ORR r1,r1,#7
00046e 8001 STRH r1,[r0,#0]
;;;1119 }
000470 bd10 POP {r4,pc}
;;;1120 /*******************************************************************************
ENDP
TIM1_UpdateDisableConfig PROC
;;;1165 /* Set or Reset the UDIS Bit */
;;;1166 *(vu32 *) CR1_UDIS_BB = (u16)Newstate;
000472 49b0 LDR r1,|L1.1844|
000474 6048 STR r0,[r1,#4]
;;;1167 }
000476 4770 BX lr
;;;1168
ENDP
TIM1_UpdateRequestConfig PROC
;;;1184 /* Set or Reset the URS Bit */
;;;1185 *(vu32 *) CR1_URS_BB = TIM1_UpdateSource;
000478 49ae LDR r1,|L1.1844|
00047a 6088 STR r0,[r1,#8]
;;;1186 }
00047c 4770 BX lr
;;;1187
ENDP
TIM1_SelectHallSensor PROC
;;;1200 /* Set or Reset the TI1S Bit */
;;;1201 *(vu32 *) CR2_TI1S_BB = (u16)Newstate;
00047e 49ae LDR r1,|L1.1848|
000480 6008 STR r0,[r1,#0]
;;;1202 }
000482 4770 BX lr
;;;1203
ENDP
TIM1_SelectOnePulseMode PROC
;;;1219 /* Set or Reset the OPM Bit */
;;;1220 *(vu32 *) CR1_OPM_BB = TIM1_OPMode;
000484 49ab LDR r1,|L1.1844|
000486 60c8 STR r0,[r1,#0xc]
;;;1221 }
000488 4770 BX lr
;;;1222
ENDP
TIM1_SelectOutputTrigger PROC
;;;1245
;;;1246 tmpcr2 = TIM1->CR2;
00048a 4aac LDR r2,|L1.1852|
00048c 8811 LDRH r1,[r2,#0]
;;;1247
;;;1248 /* Reset the MMS Bits */
;;;1249 tmpcr2 &= CR2_MMS_Mask;
00048e f001f001 AND r1,r1,#0x80
;;;1250
;;;1251 /* Select the TRGO source */
;;;1252 tmpcr2 |= TIM1_TRGOSource;
000492 4308 ORRS r0,r0,r1
;;;1253
;;;1254 TIM1->CR2 = (u16)tmpcr2;
000494 8010 STRH r0,[r2,#0]
;;;1255 }
000496 4770 BX lr
;;;1256
ENDP
TIM1_SelectSlaveMode PROC
;;;1275
;;;1276 tmpsmcr = TIM1->SMCR;
000498 4aa5 LDR r2,|L1.1840|
00049a 8811 LDRH r1,[r2,#0]
;;;1277
;;;1278 /* Reset the SMS Bits */
;;;1279 tmpsmcr &= SMCR_SMS_Mask;
00049c f64ff64f MOV r3,#0xfff0
0004a0 4019 ANDS r1,r1,r3
;;;1280
;;;1281 /* Select the Slave Mode */
;;;1282 tmpsmcr |= TIM1_SlaveMode;
0004a2 4308 ORRS r0,r0,r1
;;;1283
;;;1284 TIM1->SMCR = (u16)tmpsmcr;
0004a4 8010 STRH r0,[r2,#0]
;;;1285 }
0004a6 4770 BX lr
;;;1286
ENDP
TIM1_SelectMasterSlaveMode PROC
;;;1303 /* Set or Reset the MSM Bit */
;;;1304 *(vu32 *) SMCR_MSM_BB = TIM1_MasterSlaveMode;
0004a8 49a5 LDR r1,|L1.1856|
0004aa 6008 STR r0,[r1,#0]
;;;1305 }
0004ac 4770 BX lr
;;;1306
ENDP
TIM1_EncoderInterfaceConfig PROC
;;;1330 u16 TIM1_IC2Polarity)
;;;1331 {
0004ae b430 PUSH {r4,r5}
;;;1332 u32 tmpsmcr = 0;
;;;1333 u32 tmpccmr1 = 0;
;;;1334
;;;1335 /* Check the parameters */
;;;1336 assert(IS_TIM1_ENCODER_MODE(TIM1_EncoderMode));
;;;1337 assert(IS_TIM1_IC_POLARITY(TIM1_IC1Polarity));
;;;1338 assert(IS_TIM1_IC_POLARITY(TIM1_IC2Polarity));
;;;1339
;;;1340 tmpsmcr = TIM1->SMCR;
0004b0 4b9f LDR r3,|L1.1840|
0004b2 881c LDRH r4,[r3,#0]
;;;1341 tmpccmr1 = TIM1->CCMR1;
0004b4 f8b3f8b3 LDRH r12,[r3,#0x10]
;;;1342
;;;1343 /* Set the encoder Mode */
;;;1344 tmpsmcr &= SMCR_SMS_Mask;
0004b8 f64ff64f MOV r5,#0xfff0
0004bc 402c ANDS r4,r4,r5
;;;1345 tmpsmcr |= TIM1_EncoderMode;
0004be 4320 ORRS r0,r0,r4
;;;1346
;;;1347 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
;;;1348 tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
0004c0 f64ff64f MOV r4,#0xfcfc
0004c4 ea0cea0c AND r12,r12,r4
;;;1349 tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
0004c8 f240f240 MOV r4,#0x101
0004cc ea4cea4c ORR r12,r12,r4
;;;1350
;;;1351 /* Set the TI1 and the TI2 Polarities */
;;;1352 *(vu32 *) CCER_CC1P_BB = TIM1_IC1Polarity;
0004d0 4c9c LDR r4,|L1.1860|
0004d2 6021 STR r1,[r4,#0]
;;;1353 *(vu32 *) CCER_CC2P_BB = TIM1_IC2Polarity;
0004d4 6122 STR r2,[r4,#0x10]
;;;1354
;;;1355 TIM1->SMCR = (u16)tmpsmcr;
0004d6 8018 STRH r0,[r3,#0]
;;;1356
;;;1357 TIM1->CCMR1 = (u16)tmpccmr1;
0004d8 f8a3f8a3 STRH r12,[r3,#0x10]
;;;1358 }
0004dc bc30 POP {r4,r5}
0004de 4770 BX lr
;;;1359
ENDP
TIM1_PrescalerConfig PROC
;;;1378 /* Set the Prescaler value */
;;;1379 TIM1->PSC = Prescaler;
0004e0 4a99 LDR r2,|L1.1864|
0004e2 8010 STRH r0,[r2,#0]
;;;1380
;;;1381 /* Set or reset the UG Bit */
;;;1382 *(vu32 *) EGR_UG_BB = TIM1_PSCReloadMode;
0004e4 4893 LDR r0,|L1.1844|
0004e6 f8c0f8c0 STR r1,[r0,#0x280]
;;;1383 }
0004ea 4770 BX lr
;;;1384 /*******************************************************************************
ENDP
TIM1_CounterModeConfig PROC
;;;1403
;;;1404 tmpcr1 = TIM1->CR1;
0004ec 4a97 LDR r2,|L1.1868|
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