📄 stm32f10x_tim1.txt
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;;;654 {
00028c b570 PUSH {r4-r6,lr}
00028e 4604 MOV r4,r0
;;;655 u8 ICPolarity = TIM1_ICPolarity_Rising;
000290 2600 MOVS r6,#0
;;;656 u8 ICSelection = TIM1_ICSelection_DirectTI;
000292 2501 MOVS r5,#1
;;;657
;;;658 /* Check the parameters */
;;;659 assert(IS_TIM1_PWMI_CHANNEL(TIM1_ICInitStruct->TIM1_Channel));
;;;660 assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity));
;;;661 assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection));
;;;662 assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler));
;;;663
;;;664 /* Select the Opposite Input Polarity */
;;;665 if (TIM1_ICInitStruct->TIM1_ICPolarity == TIM1_ICPolarity_Rising)
000294 8860 LDRH r0,[r4,#2]
000296 b900 CBNZ r0,|L1.666|
;;;666 {
;;;667 ICPolarity = TIM1_ICPolarity_Falling;
000298 2601 MOVS r6,#1
|L1.666|
;;;668 }
;;;669 else
;;;670 {
;;;671 ICPolarity = TIM1_ICPolarity_Rising;
;;;672 }
;;;673
;;;674 /* Select the Opposite Input */
;;;675 if (TIM1_ICInitStruct->TIM1_ICSelection == TIM1_ICSelection_DirectTI)
00029a 88a1 LDRH r1,[r4,#4]
00029c 2901 CMP r1,#1
00029e d100 BNE |L1.674|
;;;676 {
;;;677 ICSelection = TIM1_ICSelection_IndirectTI;
0002a0 2502 MOVS r5,#2
|L1.674|
;;;678 }
;;;679 else
;;;680 {
;;;681 ICSelection = TIM1_ICSelection_DirectTI;
;;;682 }
;;;683
;;;684 if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1)
0002a2 8823 LDRH r3,[r4,#0]
0002a4 7a22 LDRB r2,[r4,#8]
0002a6 b96b CBNZ r3,|L1.708|
;;;685 {
;;;686 /* TI1 Configuration */
;;;687 TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity, TIM1_ICInitStruct->TIM1_ICSelection,
0002a8 f7fff7ff BL TI1_Config
;;;688 TIM1_ICInitStruct->TIM1_ICFilter);
;;;689
;;;690 /* Set the Input Capture Prescaler value */
;;;691 TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
0002ac 88e0 LDRH r0,[r4,#6]
0002ae f7fff7ff BL TIM1_SetIC1Prescaler
;;;692
;;;693 /* TI2 Configuration */
;;;694 TI2_Config(ICPolarity, ICSelection, TIM1_ICInitStruct->TIM1_ICFilter);
0002b2 7a22 LDRB r2,[r4,#8]
0002b4 4629 MOV r1,r5
0002b6 4630 MOV r0,r6
0002b8 f7fff7ff BL TI2_Config
;;;695
;;;696 /* Set the Input Capture Prescaler value */
;;;697 TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
0002bc 88e0 LDRH r0,[r4,#6]
0002be e8bde8bd POP {r4-r6,lr}
0002c2 e7fe B TIM1_SetIC2Prescaler
|L1.708|
;;;698 }
;;;699 else
;;;700 {
;;;701 /* TI2 Configuration */
;;;702 TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity, TIM1_ICInitStruct->TIM1_ICSelection,
0002c4 f7fff7ff BL TI2_Config
;;;703 TIM1_ICInitStruct->TIM1_ICFilter);
;;;704
;;;705 /* Set the Input Capture Prescaler value */
;;;706 TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
0002c8 88e0 LDRH r0,[r4,#6]
0002ca f7fff7ff BL TIM1_SetIC2Prescaler
;;;707
;;;708 /* TI1 Configuration */
;;;709 TI1_Config(ICPolarity, ICSelection, TIM1_ICInitStruct->TIM1_ICFilter);
0002ce 7a22 LDRB r2,[r4,#8]
0002d0 4629 MOV r1,r5
0002d2 4630 MOV r0,r6
0002d4 f7fff7ff BL TI1_Config
;;;710
;;;711 /* Set the Input Capture Prescaler value */
;;;712 TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
0002d8 88e0 LDRH r0,[r4,#6]
0002da e8bde8bd POP {r4-r6,lr}
0002de e7fe B TIM1_SetIC1Prescaler
;;;713 }
;;;714 }
;;;715 /*******************************************************************************
ENDP
TIM1_OCStructInit PROC
;;;725 /* Set the default configuration */
;;;726 TIM1_OCInitStruct->TIM1_OCMode = TIM1_OCMode_Timing;
0002e0 2100 MOVS r1,#0
0002e2 8001 STRH r1,[r0,#0]
;;;727 TIM1_OCInitStruct->TIM1_OutputState = TIM1_OutputState_Disable;
0002e4 8041 STRH r1,[r0,#2]
;;;728 TIM1_OCInitStruct->TIM1_OutputNState = TIM1_OutputNState_Disable;
0002e6 8081 STRH r1,[r0,#4]
;;;729 TIM1_OCInitStruct->TIM1_Pulse = TIM1_Pulse_Reset_Mask;
0002e8 80c1 STRH r1,[r0,#6]
;;;730 TIM1_OCInitStruct->TIM1_OCPolarity = TIM1_OCPolarity_High;
0002ea 8101 STRH r1,[r0,#8]
;;;731 TIM1_OCInitStruct->TIM1_OCNPolarity = TIM1_OCPolarity_High;
0002ec 8141 STRH r1,[r0,#0xa]
;;;732 TIM1_OCInitStruct->TIM1_OCIdleState = TIM1_OCIdleState_Reset;
0002ee 8181 STRH r1,[r0,#0xc]
;;;733 TIM1_OCInitStruct->TIM1_OCNIdleState = TIM1_OCNIdleState_Reset;
0002f0 81c1 STRH r1,[r0,#0xe]
;;;734 }
0002f2 4770 BX lr
;;;735
ENDP
TIM1_ICStructInit PROC
;;;746 /* Set the default configuration */
;;;747 TIM1_ICInitStruct->TIM1_Channel = TIM1_Channel_1;
0002f4 2100 MOVS r1,#0
0002f6 8001 STRH r1,[r0,#0]
;;;748 TIM1_ICInitStruct->TIM1_ICSelection = TIM1_ICSelection_DirectTI;
0002f8 2201 MOVS r2,#1
0002fa 8082 STRH r2,[r0,#4]
;;;749 TIM1_ICInitStruct->TIM1_ICPolarity = TIM1_ICPolarity_Rising;
0002fc 8041 STRH r1,[r0,#2]
;;;750 TIM1_ICInitStruct->TIM1_ICPrescaler = TIM1_ICPSC_DIV1;
0002fe 80c1 STRH r1,[r0,#6]
;;;751 TIM1_ICInitStruct->TIM1_ICFilter = TIM1_ICFilter_Mask;
000300 7201 STRB r1,[r0,#8]
;;;752 }
000302 4770 BX lr
;;;753
ENDP
TIM1_TimeBaseStructInit PROC
;;;764 /* Set the default configuration */
;;;765 TIM1_TimeBaseInitStruct->TIM1_Period = TIM1_Period_Reset_Mask;
000304 f64ff64f MOV r1,#0xffff
000308 8081 STRH r1,[r0,#4]
;;;766 TIM1_TimeBaseInitStruct->TIM1_Prescaler = TIM1_Prescaler_Reset_Mask;
00030a 2100 MOVS r1,#0
00030c 8001 STRH r1,[r0,#0]
;;;767 TIM1_TimeBaseInitStruct->TIM1_ClockDivision = TIM1_CKD_DIV1;
00030e 80c1 STRH r1,[r0,#6]
;;;768 TIM1_TimeBaseInitStruct->TIM1_CounterMode = TIM1_CounterMode_Up;
000310 8041 STRH r1,[r0,#2]
;;;769 TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter = TIM1_RepetitionCounter_Reset_Mask;
000312 7201 STRB r1,[r0,#8]
;;;770 }
000314 4770 BX lr
;;;771
ENDP
TIM1_BDTRStructInit PROC
;;;782 /* Set the default configuration */
;;;783 TIM1_BDTRInitStruct->TIM1_OSSRState = TIM1_OSSRState_Disable;
000316 2100 MOVS r1,#0
000318 8001 STRH r1,[r0,#0]
;;;784 TIM1_BDTRInitStruct->TIM1_OSSIState = TIM1_OSSIState_Disable;
00031a 8041 STRH r1,[r0,#2]
;;;785 TIM1_BDTRInitStruct->TIM1_LOCKLevel = TIM1_LOCKLevel_OFF;
00031c 8081 STRH r1,[r0,#4]
;;;786 TIM1_BDTRInitStruct->TIM1_DeadTime = TIM1_DeadTime_Reset_Mask;
00031e 80c1 STRH r1,[r0,#6]
;;;787 TIM1_BDTRInitStruct->TIM1_Break = TIM1_Break_Disable;
000320 8101 STRH r1,[r0,#8]
;;;788 TIM1_BDTRInitStruct->TIM1_BreakPolarity = TIM1_BreakPolarity_Low;
000322 8141 STRH r1,[r0,#0xa]
;;;789 TIM1_BDTRInitStruct->TIM1_AutomaticOutput = TIM1_AutomaticOutput_Disable;
000324 8181 STRH r1,[r0,#0xc]
;;;790 }
000326 4770 BX lr
;;;791
ENDP
TIM1_Cmd PROC
;;;805 /* set or Reset the CEN Bit */
;;;806 *(vu32 *) CR1_CEN_BB = (u16)NewState;
000328 4942 LDR r1,|L1.1076|
00032a 6008 STR r0,[r1,#0]
;;;807 }
00032c 4770 BX lr
;;;808
ENDP
TIM1_CtrlPWMOutputs PROC
;;;822 /* Set or Reset the MOE Bit */
;;;823 *(vu32 *) BDTR_MOE_BB = (u16)Newstate;
00032e 4942 LDR r1,|L1.1080|
000330 6008 STR r0,[r1,#0]
;;;824 }
000332 4770 BX lr
;;;825
ENDP
TIM1_ITConfig PROC
;;;851
;;;852 if (NewState == ENABLE)
000334 4a3a LDR r2,|L1.1056|
000336 2901 CMP r1,#1
000338 d105 BNE |L1.838|
;;;853 {
;;;854 /* Enable the Interrupt sources */
;;;855 TIM1->DIER |= TIM1_IT;
00033a f8b2f8b2 LDRH r1,[r2,#0xc0c]
00033e 4308 ORRS r0,r0,r1
000340 f8a2f8a2 STRH r0,[r2,#0xc0c]
;;;856 }
;;;857 else
;;;858 {
;;;859 /* Disable the Interrupt sources */
;;;860 TIM1->DIER &= (u16)~TIM1_IT;
;;;861 }
;;;862 }
000344 4770 BX lr
|L1.838|
000346 f8b2f8b2 LDRH r1,[r2,#0xc0c]
00034a ea21ea21 BIC r0,r1,r0
00034e f8a2f8a2 STRH r0,[r2,#0xc0c]
000352 4770 BX lr
;;;863
ENDP
TIM1_DMAConfig PROC
;;;889
;;;890 tmpdcr = TIM1->DCR;
000354 4a39 LDR r2,|L1.1084|
000356 8813 LDRH r3,[r2,#0]
;;;891
;;;892 /* Reset the DBA and the DBL Bits */
;;;893 tmpdcr &= DCR_DMA_Mask;
;;;894
;;;895 /* Set the DMA Base and the DMA Burst Length */
;;;896 tmpdcr |= TIM1_DMABase | TIM1_DMABurstLength;
000358 4308 ORRS r0,r0,r1
;;;897
;;;898 TIM1->DCR = (u16)tmpdcr;
00035a 8010 STRH r0,[r2,#0]
;;;899 }
00035c 4770 BX lr
;;;900
ENDP
TIM1_DMACmd PROC
;;;926
;;;927 tmpdier = TIM1->DIER;
00035e 4b30 LDR r3,|L1.1056|
000360 f8b3f8b3 LDRH r2,[r3,#0xc0c]
;;;928
;;;929 if (Newstate == ENABLE)
000364 2901 CMP r1,#1
000366 d101 BNE |L1.876|
;;;930 {
;;;931 /* Enable the DMA sources */
;;;932 tmpdier |= TIM1_DMASource;
000368 4310 ORRS r0,r0,r2
00036a e002 B |L1.882|
|L1.876|
;;;933 }
;;;934 else
;;;935 {
;;;936 /* Disable the DMA sources */
;;;937 tmpdier &= (u16)~TIM1_DMASource;
00036c 43c0 MVNS r0,r0
00036e b280 UXTH r0,r0
000370 4010 ANDS r0,r0,r2
|L1.882|
;;;938 }
;;;939 TIM1->DIER = (u16)tmpdier;
000372 f8a3f8a3 STRH r0,[r3,#0xc0c]
;;;940 }
000376 4770 BX lr
;;;941
ENDP
TIM1_InternalClockConfig PROC
;;;951 /* Disable slave mode to clock the prescaler directly with the internal clock */
;;;952 TIM1->SMCR &= SMCR_SMS_Mask;
000378 4831 LDR r0,|L1.1088|
00037a 8801 LDRH r1,[r0,#0]
00037c f021f021 BIC r1,r1,#0xf
000380 8001 STRH r1,[r0,#0]
;;;953 }
000382 4770 BX lr
;;;954 /*******************************************************************************
ENDP
TIM1_ETRConfig PROC
;;;1042 u16 ExtTRGFilter)
;;;1043 {
000384 b410 PUSH {r4}
;;;1044 u32 tmpsmcr = 0;
;;;1045
;;;1046 tmpsmcr = TIM1->SMCR;
000386 f8dff8df LDR r12,|L1.1056|
00038a f8bcf8bc LDRH r3,[r12,#0xc08]
;;;1047
;;;1048 /* Set the Prescaler, the Filter value and the Polarity */
;;;1049 tmpsmcr &= SMCR_ETR_Mask;
00038e f244f244 MOV r4,#0x40f7
000392 4023 ANDS r3,r3,r4
;;;1050 tmpsmcr |= TIM1_ExtTRGPrescaler | TIM1_ExtTRGPolarity | (u16)((u16)ExtTRGFilter << 8);
000394 4301 ORRS r1,r1,r0
000396 ea41ea41 ORR r0,r1,r2,LSL #8
00039a 4318 ORRS r0,r0,r3
;;;1051
;;;1052 TIM1->SMCR = (u16)tmpsmcr;
00039c f8acf8ac STRH r0,[r12,#0xc08]
;;;1053 }
0003a0 bc10 POP {r4}
0003a2 4770 BX lr
;;;1054
ENDP
TIM1_ETRClockMode1Config PROC
;;;973 u16 ExtTRGFilter)
;;;974 {
0003a4 b500 PUSH {lr}
;;;975 /* Check the parameters */
;;;976 assert(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler));
;;;977 assert(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity));
;;;978
;;;979 /* Configure the ETR Clock source */
;;;980 TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
0003a6 f7fff7ff BL TIM1_ETRConfig
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