📄 stm32f10x_tim1.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 914] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\rvmdk\stm32f10x_tim1.o --depend=.\rvmdk\stm32f10x_tim1.d --device=DARMSTM -O1 -Otime -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -I..\..\..\..\..\uC-Probe\Target\Plugins\uCOS-II -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\Source -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Ports\ST\STM32 -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Source -ID:\Keil\ARM\INC\ST\STM32F10x ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_tim1.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
TIM1_DeInit PROC
;;;294 void TIM1_DeInit(void)
;;;295 {
000000 b510 PUSH {r4,lr}
;;;296 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
000002 2101 MOVS r1,#1
000004 02c8 LSLS r0,r1,#11
000006 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;297 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
00000a e8bde8bd POP {r4,lr}
00000e 2100 MOVS r1,#0
000010 f44ff44f MOV r0,#0x800
000014 f7fff7ff B.W RCC_APB2PeriphResetCmd
;;;298 }
;;;299
ENDP
TIM1_TimeBaseInit PROC
;;;316 /* Set the Autoreload value */
;;;317 TIM1->ARR = TIM1_TimeBaseInitStruct->TIM1_Period ;
000018 49f9 LDR r1,|L1.1024|
00001a 8882 LDRH r2,[r0,#4]
00001c 858a STRH r2,[r1,#0x2c]
;;;318
;;;319 /* Set the Prescaler value */
;;;320 TIM1->PSC = TIM1_TimeBaseInitStruct->TIM1_Prescaler;
00001e 8802 LDRH r2,[r0,#0]
000020 850a STRH r2,[r1,#0x28]
;;;321
;;;322 /* Select the Counter Mode and set the clock division */
;;;323 TIM1->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
000022 880a LDRH r2,[r1,#0]
000024 f002f002 AND r2,r2,#0x9f
000028 800a STRH r2,[r1,#0]
;;;324 TIM1->CR1 |= (u32)TIM1_TimeBaseInitStruct->TIM1_ClockDivision |
00002a 88c2 LDRH r2,[r0,#6]
00002c 8843 LDRH r3,[r0,#2]
00002e 431a ORRS r2,r2,r3
000030 880b LDRH r3,[r1,#0]
000032 431a ORRS r2,r2,r3
000034 800a STRH r2,[r1,#0]
;;;325 TIM1_TimeBaseInitStruct->TIM1_CounterMode;
;;;326
;;;327 /* Set the Repetition Counter value */
;;;328 TIM1->RCR = TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter;
000036 7a00 LDRB r0,[r0,#8]
000038 8608 STRH r0,[r1,#0x30]
;;;329 }
00003a 4770 BX lr
;;;330
ENDP
TIM1_OC1Init PROC
;;;352
;;;353 tmpccmr = TIM1->CCMR1;
00003c 4bf1 LDR r3,|L1.1028|
00003e 881a LDRH r2,[r3,#0]
;;;354
;;;355 /* Disable the Channel 1: Reset the CCE Bit */
;;;356 *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;
000040 49f1 LDR r1,|L1.1032|
000042 f04ff04f MOV r12,#0
000046 f8c1f8c1 STR r12,[r1,#0x360]
;;;357
;;;358 /* Reset the Output Compare Bits */
;;;359 tmpccmr &= OC13Mode_Mask;
00004a f402f402 AND r2,r2,#0xff00
;;;360
;;;361 /* Set the Ouput Compare Mode */
;;;362 tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
00004e f8b0f8b0 LDRH r12,[r0,#0]
000052 ea4cea4c ORR r2,r12,r2
;;;363
;;;364 TIM1->CCMR1 = tmpccmr;
000056 801a STRH r2,[r3,#0]
;;;365
;;;366 /* Set the Output State */
;;;367 *(vu32 *) CCER_CC1E_BB = TIM1_OCInitStruct->TIM1_OutputState;
000058 8842 LDRH r2,[r0,#2]
00005a f8c1f8c1 STR r2,[r1,#0x360]
;;;368
;;;369 /* Set the Output N State */
;;;370 *(vu32 *) CCER_CC1NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
00005e 8882 LDRH r2,[r0,#4]
000060 f8c1f8c1 STR r2,[r1,#0x368]
;;;371
;;;372 /* Set the Output Polarity */
;;;373 *(vu32 *) CCER_CC1P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
000064 8902 LDRH r2,[r0,#8]
000066 f8c1f8c1 STR r2,[r1,#0x364]
;;;374
;;;375 /* Set the Output N Polarity */
;;;376 *(vu32 *) CCER_CC1NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
00006a 8942 LDRH r2,[r0,#0xa]
00006c f8c1f8c1 STR r2,[r1,#0x36c]
;;;377
;;;378 /* Set the Output Idle state */
;;;379 *(vu32 *) CR2_OIS1_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
000070 8982 LDRH r2,[r0,#0xc]
000072 600a STR r2,[r1,#0]
;;;380
;;;381 /* Set the Output N Idle state */
;;;382 *(vu32 *) CR2_OIS1N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
000074 89c2 LDRH r2,[r0,#0xe]
000076 604a STR r2,[r1,#4]
;;;383
;;;384 /* Set the Pulse value */
;;;385 TIM1->CCR1 = TIM1_OCInitStruct->TIM1_Pulse;
000078 88c0 LDRH r0,[r0,#6]
00007a 8398 STRH r0,[r3,#0x1c]
;;;386 }
00007c 4770 BX lr
;;;387
ENDP
TIM1_OC2Init PROC
;;;409
;;;410 tmpccmr = TIM1->CCMR1;
00007e 4be1 LDR r3,|L1.1028|
000080 881a LDRH r2,[r3,#0]
;;;411
;;;412 /* Disable the Channel 2: Reset the CCE Bit */
;;;413 *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;
000082 49e2 LDR r1,|L1.1036|
000084 f04ff04f MOV r12,#0
000088 f8c1f8c1 STR r12,[r1,#0x368]
;;;414
;;;415 /* Reset the Output Compare Bits */
;;;416 tmpccmr &= OC24Mode_Mask;
00008c b2d2 UXTB r2,r2
;;;417
;;;418 /* Set the Ouput Compare Mode */
;;;419 tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
00008e f8b0f8b0 LDRH r12,[r0,#0]
000092 ea42ea42 ORR r2,r2,r12,LSL #8
;;;420
;;;421 TIM1->CCMR1 = (u16)tmpccmr;
000096 801a STRH r2,[r3,#0]
;;;422
;;;423 /* Set the Output State */
;;;424 *(vu32 *) CCER_CC2E_BB = TIM1_OCInitStruct->TIM1_OutputState;
000098 8842 LDRH r2,[r0,#2]
00009a f8c1f8c1 STR r2,[r1,#0x368]
;;;425
;;;426 /* Set the Output N State */
;;;427 *(vu32 *) CCER_CC2NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
00009e 8882 LDRH r2,[r0,#4]
0000a0 f8c1f8c1 STR r2,[r1,#0x370]
;;;428
;;;429 /* Set the Output Polarity */
;;;430 *(vu32 *) CCER_CC2P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
0000a4 8902 LDRH r2,[r0,#8]
0000a6 f8c1f8c1 STR r2,[r1,#0x36c]
;;;431
;;;432 /* Set the Output N Polarity */
;;;433 *(vu32 *) CCER_CC2NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
0000aa 8942 LDRH r2,[r0,#0xa]
0000ac f8c1f8c1 STR r2,[r1,#0x374]
;;;434
;;;435 /* Set the Output Idle state */
;;;436 *(vu32 *) CR2_OIS2_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
0000b0 8982 LDRH r2,[r0,#0xc]
0000b2 600a STR r2,[r1,#0]
;;;437
;;;438 /* Set the Output N Idle state */
;;;439 *(vu32 *) CR2_OIS2N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
0000b4 89c2 LDRH r2,[r0,#0xe]
0000b6 604a STR r2,[r1,#4]
;;;440
;;;441 /* Set the Pulse value */
;;;442 TIM1->CCR2 = TIM1_OCInitStruct->TIM1_Pulse;
0000b8 88c0 LDRH r0,[r0,#6]
0000ba 8418 STRH r0,[r3,#0x20]
;;;443 }
0000bc 4770 BX lr
;;;444
ENDP
TIM1_OC3Init PROC
;;;466
;;;467 tmpccmr = TIM1->CCMR2;
0000be 4bd4 LDR r3,|L1.1040|
0000c0 881a LDRH r2,[r3,#0]
;;;468
;;;469 /* Disable the Channel 3: Reset the CCE Bit */
;;;470 *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;
0000c2 49d4 LDR r1,|L1.1044|
0000c4 f04ff04f MOV r12,#0
0000c8 f8c1f8c1 STR r12,[r1,#0x370]
;;;471
;;;472 /* Reset the Output Compare Bits */
;;;473 tmpccmr &= OC13Mode_Mask;
0000cc f402f402 AND r2,r2,#0xff00
;;;474
;;;475 /* Set the Ouput Compare Mode */
;;;476 tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
0000d0 f8b0f8b0 LDRH r12,[r0,#0]
0000d4 ea4cea4c ORR r2,r12,r2
;;;477
;;;478 TIM1->CCMR2 = tmpccmr;
0000d8 801a STRH r2,[r3,#0]
;;;479
;;;480 /* Set the Output State */
;;;481 *(vu32 *) CCER_CC3E_BB = TIM1_OCInitStruct->TIM1_OutputState;
0000da 8842 LDRH r2,[r0,#2]
0000dc f8c1f8c1 STR r2,[r1,#0x370]
;;;482
;;;483 /* Set the Output N State */
;;;484 *(vu32 *) CCER_CC3NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
0000e0 8882 LDRH r2,[r0,#4]
0000e2 f8c1f8c1 STR r2,[r1,#0x378]
;;;485
;;;486 /* Set the Output Polarity */
;;;487 *(vu32 *) CCER_CC3P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
0000e6 8902 LDRH r2,[r0,#8]
0000e8 f8c1f8c1 STR r2,[r1,#0x374]
;;;488
;;;489 /* Set the Output N Polarity */
;;;490 *(vu32 *) CCER_CC3NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
0000ec 8942 LDRH r2,[r0,#0xa]
0000ee f8c1f8c1 STR r2,[r1,#0x37c]
;;;491
;;;492 /* Set the Output Idle state */
;;;493 *(vu32 *) CR2_OIS3_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
0000f2 8982 LDRH r2,[r0,#0xc]
0000f4 600a STR r2,[r1,#0]
;;;494
;;;495 /* Set the Output N Idle state */
;;;496 *(vu32 *) CR2_OIS3N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
0000f6 89c2 LDRH r2,[r0,#0xe]
0000f8 604a STR r2,[r1,#4]
;;;497
;;;498 /* Set the Pulse value */
;;;499 TIM1->CCR3 = TIM1_OCInitStruct->TIM1_Pulse;
0000fa 88c0 LDRH r0,[r0,#6]
0000fc 8418 STRH r0,[r3,#0x20]
;;;500 }
0000fe 4770 BX lr
;;;501
ENDP
TIM1_OC4Init PROC
;;;520
;;;521 tmpccmr = TIM1->CCMR2;
000100 4bc3 LDR r3,|L1.1040|
000102 881a LDRH r2,[r3,#0]
;;;522
;;;523 /* Disable the Channel 4: Reset the CCE Bit */
;;;524 *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;
000104 49c4 LDR r1,|L1.1048|
000106 f04ff04f MOV r12,#0
00010a f8c1f8c1 STR r12,[r1,#0x3b4]
;;;525
;;;526 /* Reset the Output Compare Bits */
;;;527 tmpccmr &= OC24Mode_Mask;
00010e b2d2 UXTB r2,r2
;;;528
;;;529 /* Set the Ouput Compare Mode */
;;;530 tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
000110 f8b0f8b0 LDRH r12,[r0,#0]
000114 ea42ea42 ORR r2,r2,r12,LSL #8
;;;531
;;;532 TIM1->CCMR2 = (u16)tmpccmr;
000118 801a STRH r2,[r3,#0]
;;;533
;;;534 /* Set the Output State */
;;;535 *(vu32 *) CCER_CC4E_BB = TIM1_OCInitStruct->TIM1_OutputState;
00011a 8842 LDRH r2,[r0,#2]
00011c f8c1f8c1 STR r2,[r1,#0x3b4]
;;;536
;;;537 /* Set the Output Polarity */
;;;538 *(vu32 *) CCER_CC4P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
000120 8902 LDRH r2,[r0,#8]
000122 f8c1f8c1 STR r2,[r1,#0x3b8]
;;;539
;;;540 /* Set the Output Idle state */
;;;541 *(vu32 *) CR2_OIS4_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
000126 8982 LDRH r2,[r0,#0xc]
000128 63ca STR r2,[r1,#0x3c]
;;;542
;;;543 /* Set the Pulse value */
;;;544 TIM1->CCR4 = TIM1_OCInitStruct->TIM1_Pulse;
00012a 88c0 LDRH r0,[r0,#6]
00012c 8498 STRH r0,[r3,#0x24]
;;;545 }
00012e 4770 BX lr
;;;546
ENDP
TIM1_BDTRConfig PROC
;;;568
;;;569 tmpbdtr = TIM1->BDTR;
000130 49ba LDR r1,|L1.1052|
000132 880a LDRH r2,[r1,#0]
;;;570
;;;571 /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
;;;572 the OSSI State, the dead time value and the Automatic Output Enable Bit */
;;;573
;;;574 tmpbdtr = (u32)TIM1_BDTRInitStruct->TIM1_OSSRState | TIM1_BDTRInitStruct->TIM1_OSSIState |
000134 8802 LDRH r2,[r0,#0]
000136 8843 LDRH r3,[r0,#2]
000138 f8b0f8b0 LDRH r12,[r0,#6]
00013c 431a ORRS r2,r2,r3
00013e 8883 LDRH r3,[r0,#4]
000140 ea43ea43 ORR r3,r3,r12
000144 431a ORRS r2,r2,r3
000146 8903 LDRH r3,[r0,#8]
000148 431a ORRS r2,r2,r3
00014a 8943 LDRH r3,[r0,#0xa]
00014c 8980 LDRH r0,[r0,#0xc]
00014e 431a ORRS r2,r2,r3
000150 4310 ORRS r0,r0,r2
;;;575 TIM1_BDTRInitStruct->TIM1_LOCKLevel | TIM1_BDTRInitStruct->TIM1_DeadTime |
;;;576 TIM1_BDTRInitStruct->TIM1_Break | TIM1_BDTRInitStruct->TIM1_BreakPolarity |
;;;577 TIM1_BDTRInitStruct->TIM1_AutomaticOutput;
;;;578
;;;579 TIM1->BDTR = tmpbdtr;
000152 8008 STRH r0,[r1,#0]
;;;580 }
000154 4770 BX lr
;;;581
ENDP
TIM1_SetIC4Prescaler PROC
;;;2342
;;;2343 tmpccmr2 = TIM1->CCMR2;
000156 4aae LDR r2,|L1.1040|
000158 8811 LDRH r1,[r2,#0]
;;;2344
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