📄 stm32f10x_nvic.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 914] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\rvmdk\stm32f10x_nvic.o --depend=.\rvmdk\stm32f10x_nvic.d --device=DARMSTM -O1 -Otime -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -I..\..\..\..\..\uC-Probe\Target\Plugins\uCOS-II -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\Source -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Ports\ST\STM32 -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Source -ID:\Keil\ARM\INC\ST\STM32F10x ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_nvic.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
NVIC_DeInit PROC
;;;42 {
;;;43 u32 index = 0;
000000 2000 MOVS r0,#0
;;;44
;;;45 NVIC->Disable[0] = 0xFFFFFFFF;
000002 1e43 SUBS r3,r0,#1
000004 f04ff04f MOV r1,#0xe000e000
000008 f8c1f8c1 STR r3,[r1,#0x180]
;;;46 NVIC->Disable[1] = 0x000007FF;
00000c 0d5a LSRS r2,r3,#21
00000e f8c1f8c1 STR r2,[r1,#0x184]
;;;47 NVIC->Clear[0] = 0xFFFFFFFF;
000012 f8c1f8c1 STR r3,[r1,#0x280]
;;;48 NVIC->Clear[1] = 0x000007FF;
000016 f8c1f8c1 STR r2,[r1,#0x284]
;;;49
;;;50 for(index = 0; index < 0x0B; index++)
00001a 2200 MOVS r2,#0
|L1.28|
00001c eb01eb01 ADD r3,r1,r0,LSL #2
000020 f8c3f8c3 STR r2,[r3,#0x400]
000024 1c40 ADDS r0,r0,#1
000026 280b CMP r0,#0xb
000028 d3f8 BCC |L1.28|
;;;51 {
;;;52 NVIC->Priority[index] = 0x00000000;
;;;53 }
;;;54 }
00002a 4770 BX lr
;;;55
ENDP
NVIC_SCBDeInit PROC
;;;65 {
;;;66 u32 index = 0x00;
00002c 2000 MOVS r0,#0
;;;67
;;;68 SCB->IRQControlState = 0x0A000000;
00002e f04ff04f MOV r1,#0xa000000
000032 f04ff04f MOV r2,#0xe000e000
000036 f8c2f8c2 STR r1,[r2,#0xd04]
;;;69 SCB->ExceptionTableOffset = 0x00000000;
00003a 2100 MOVS r1,#0
00003c f8c2f8c2 STR r1,[r2,#0xd08]
;;;70 SCB->AIRC = AIRC_VECTKEY_MASK;
000040 4bb8 LDR r3,|L1.804|
000042 f8c2f8c2 STR r3,[r2,#0xd0c]
;;;71 SCB->SysCtrl = 0x00000000;
000046 f8c2f8c2 STR r1,[r2,#0xd10]
;;;72 SCB->ConfigCtrl = 0x00000000;
00004a f8c2f8c2 STR r1,[r2,#0xd14]
|L1.78|
00004e eb02eb02 ADD r3,r2,r0,LSL #2
000052 f8c3f8c3 STR r1,[r3,#0xd18]
;;;73 for(index = 0; index < 0x03; index++)
000056 1c40 ADDS r0,r0,#1
000058 2803 CMP r0,#3
00005a d3f8 BCC |L1.78|
;;;74 {
;;;75 SCB->SystemPriority[index] = 0;
;;;76 }
;;;77 SCB->SysHandlerCtrl = 0x00000000;
00005c f8c2f8c2 STR r1,[r2,#0xd24]
;;;78 SCB->ConfigFaultStatus = 0xFFFFFFFF;
000060 f04ff04f MOV r0,#0xffffffff
000064 f8c2f8c2 STR r0,[r2,#0xd28]
;;;79 SCB->HardFaultStatus = 0xFFFFFFFF;
000068 f8c2f8c2 STR r0,[r2,#0xd2c]
;;;80 SCB->DebugFaultStatus = 0xFFFFFFFF;
00006c f8c2f8c2 STR r0,[r2,#0xd30]
;;;81 }
000070 4770 BX lr
;;;82
ENDP
NVIC_PriorityGroupConfig PROC
;;;107 /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
;;;108 SCB->AIRC = AIRC_VECTKEY_MASK | NVIC_PriorityGroup;
000072 f040f040 ORR r0,r0,#0x1fa0000
000076 49ac LDR r1,|L1.808|
000078 f040f040 ORR r0,r0,#0x4000000
00007c 6008 STR r0,[r1,#0]
;;;109 }
00007e 4770 BX lr
;;;110
ENDP
NVIC_Init PROC
;;;121 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
;;;122 {
000080 b470 PUSH {r4-r6}
;;;123 u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00;
;;;124 u32 tmppre = 0, tmpsub = 0x0F;
000082 f04ff04f MOV r12,#0xf
;;;125
;;;126 /* Check the parameters */
;;;127 assert(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
;;;128 assert(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel));
;;;129 assert(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
;;;130 assert(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
;;;131
;;;132 if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
000086 78c2 LDRB r2,[r0,#3]
000088 7801 LDRB r1,[r0,#0]
00008a f04ff04f MOV r5,#0xe000e000
00008e 2601 MOVS r6,#1
000090 b37a CBZ r2,|L1.242|
;;;133 {
;;;134 /* Compute the Corresponding IRQ Priority --------------------------------*/
;;;135 tmppriority = (0x700 - (SCB->AIRC & (u32)0x700))>> 0x08;
000092 f8d5f8d5 LDR r2,[r5,#0xd0c]
000096 f402f402 AND r2,r2,#0x700
00009a f5c2f5c2 RSB r2,r2,#0x700
00009e 0a12 LSRS r2,r2,#8
;;;136 tmppre = (0x4 - tmppriority);
0000a0 f1c2f1c2 RSB r3,r2,#4
;;;137 tmpsub = tmpsub >> tmppriority;
0000a4 fa2cfa2c LSR r12,r12,r2
;;;138
;;;139 tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
0000a8 7842 LDRB r2,[r0,#1]
0000aa 409a LSLS r2,r2,r3
;;;140 tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
0000ac 7883 LDRB r3,[r0,#2]
0000ae ea03ea03 AND r3,r3,r12
0000b2 431a ORRS r2,r2,r3
;;;141
;;;142 tmppriority = tmppriority << 0x04;
0000b4 0113 LSLS r3,r2,#4
;;;143 tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
0000b6 078a LSLS r2,r1,#30
0000b8 0ed2 LSRS r2,r2,#27
0000ba fa03fa03 LSL r12,r3,r2
;;;144
;;;145 tmpreg = NVIC->Priority[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)];
0000be f021f021 BIC r1,r1,#3
0000c2 194b ADDS r3,r1,r5
0000c4 f8d3f8d3 LDR r4,[r3,#0x400]
;;;146 tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
0000c8 21ff MOVS r1,#0xff
0000ca 4091 LSLS r1,r1,r2
;;;147 tmpreg &= ~tmpmask;
0000cc ea24ea24 BIC r2,r4,r1
;;;148 tmppriority &= tmpmask;
0000d0 ea0cea0c AND r1,r12,r1
;;;149 tmpreg |= tmppriority;
0000d4 4311 ORRS r1,r1,r2
;;;150
;;;151 NVIC->Priority[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg;
0000d6 f8c3f8c3 STR r1,[r3,#0x400]
;;;152
;;;153 /* Enable the Selected IRQ Channels --------------------------------------*/
;;;154 NVIC->Enable[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
0000da 7800 LDRB r0,[r0,#0]
0000dc f000f000 AND r1,r0,#0x1f
0000e0 fa06fa06 LSL r1,r6,r1
0000e4 0940 LSRS r0,r0,#5
0000e6 eb05eb05 ADD r0,r5,r0,LSL #2
0000ea f8c0f8c0 STR r1,[r0,#0x100]
0000ee bc70 POP {r4-r6}
0000f0 4770 BX lr
|L1.242|
;;;155 (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
;;;156 }
;;;157 else
;;;158 {
;;;159 /* Disable the Selected IRQ Channels -------------------------------------*/
;;;160 NVIC->Disable[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
;;;161 (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
;;;162 }
;;;163 }
0000f2 e7ff B |L1.244|
|L1.244|
0000f4 f001f001 AND r0,r1,#0x1f
0000f8 fa06fa06 LSL r0,r6,r0
0000fc 0949 LSRS r1,r1,#5
0000fe eb05eb05 ADD r1,r5,r1,LSL #2
000102 f8c1f8c1 STR r0,[r1,#0x180]
000106 bc70 POP {r4-r6}
000108 4770 BX lr
;;;164
ENDP
NVIC_StructInit PROC
;;;175 /* NVIC_InitStruct members default value */
;;;176 NVIC_InitStruct->NVIC_IRQChannel = 0x00;
00010a 2100 MOVS r1,#0
00010c 7001 STRB r1,[r0,#0]
;;;177 NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00;
00010e 7041 STRB r1,[r0,#1]
;;;178 NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00;
000110 7081 STRB r1,[r0,#2]
;;;179 NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE;
000112 70c1 STRB r1,[r0,#3]
;;;180 }
000114 4770 BX lr
;;;181
ENDP
NVIC_SETPRIMASK PROC
;;;190 {
;;;191 __SETPRIMASK();
000116 f7fff7ff B.W __SETPRIMASK
;;;192 }
;;;193
ENDP
NVIC_RESETPRIMASK PROC
;;;202 {
;;;203 __RESETPRIMASK();
00011a f7fff7ff B.W __RESETPRIMASK
;;;204 }
;;;205
ENDP
NVIC_SETFAULTMASK PROC
;;;214 {
;;;215 __SETFAULTMASK();
00011e f7fff7ff B.W __SETFAULTMASK
;;;216 }
;;;217
ENDP
NVIC_RESETFAULTMASK PROC
;;;226 {
;;;227 __RESETFAULTMASK();
000122 f7fff7ff B.W __RESETFAULTMASK
;;;228 }
;;;229
ENDP
NVIC_BASEPRICONFIG PROC
;;;242
;;;243 __BASEPRICONFIG(NewPriority << 0x04);
000126 0100 LSLS r0,r0,#4
000128 f7fff7ff B.W __BASEPRICONFIG
;;;244 }
;;;245
ENDP
NVIC_GetBASEPRI PROC
;;;254 {
;;;255 return (__GetBASEPRI());
00012c f7fff7ff B.W __GetBASEPRI
;;;256 }
;;;257
ENDP
NVIC_GetCurrentPendingIRQChannel PROC
;;;266 {
;;;267 return ((u16)((SCB->IRQControlState & (u32)0x003FF000) >> 0x0C));
000130 487e LDR r0,|L1.812|
000132 6800 LDR r0,[r0,#0]
000134 f3c0f3c0 UBFX r0,r0,#12,#10
;;;268 }
000138 4770 BX lr
;;;269
ENDP
NVIC_GetIRQChannelPendingBitStatus PROC
;;;279 {
;;;280 ITStatus pendingirqstatus = RESET;
00013a 2100 MOVS r1,#0
;;;281 u32 tmp = 0x00;
;;;282
;;;283 /* Check the parameters */
;;;284 assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
;;;285
;;;286 tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
00013c f000f000 AND r2,r0,#0x1f
000140 2301 MOVS r3,#1
000142 fa03fa03 LSL r2,r3,r2
;;;287
;;;288 if (((NVIC->Set[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp)
000146 0940 LSRS r0,r0,#5
000148 f04ff04f MOV r3,#0xe000e000
00014c eb03eb03 ADD r0,r3,r0,LSL #2
000150 f8d0f8d0 LDR r0,[r0,#0x200]
000154 ea32ea32 BICS r0,r2,r0
000158 d100 BNE |L1.348|
;;;289 {
;;;290 pendingirqstatus = SET;
00015a 2101 MOVS r1,#1
|L1.348|
;;;291 }
;;;292 else
;;;293 {
;;;294 pendingirqstatus = RESET;
;;;295 }
;;;296 return pendingirqstatus;
00015c 4608 MOV r0,r1
;;;297 }
00015e 4770 BX lr
;;;298
ENDP
NVIC_SetIRQChannelPendingBit PROC
;;;310
;;;311 *(u32*)0xE000EF00 = (u32)NVIC_IRQChannel;
000160 4973 LDR r1,|L1.816|
000162 6008 STR r0,[r1,#0]
;;;312 }
000164 4770 BX lr
;;;313
ENDP
NVIC_ClearIRQChannelPendingBit PROC
;;;325
;;;326 NVIC->Clear[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F);
000166 f000f000 AND r1,r0,#0x1f
00016a 2201 MOVS r2,#1
00016c fa02fa02 LSL r1,r2,r1
000170 0940 LSRS r0,r0,#5
000172 f04ff04f MOV r2,#0xe000e000
000176 eb02eb02 ADD r0,r2,r0,LSL #2
00017a f8c0f8c0 STR r1,[r0,#0x280]
;;;327 }
00017e 4770 BX lr
;;;328
ENDP
NVIC_GetCurrentActiveHandler PROC
;;;338 {
;;;339 return ((u16)(SCB->IRQControlState & (u32)0x3FF));
000180 486a LDR r0,|L1.812|
000182 6800 LDR r0,[r0,#0]
000184 f3c0f3c0 UBFX r0,r0,#0,#10
;;;340 }
000188 4770 BX lr
;;;341
ENDP
NVIC_GetIRQChannelActiveBitStatus PROC
;;;351 {
;;;352 ITStatus activeirqstatus = RESET;
00018a 2100 MOVS r1,#0
;;;353 u32 tmp = 0x00;
;;;354
;;;355 /* Check the parameters */
;;;356 assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
;;;357
;;;358 tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
00018c f000f000 AND r2,r0,#0x1f
000190 2301 MOVS r3,#1
000192 fa03fa03 LSL r2,r3,r2
;;;359
;;;360 if (((NVIC->Active[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp )
000196 0940 LSRS r0,r0,#5
000198 f04ff04f MOV r3,#0xe000e000
00019c eb03eb03 ADD r0,r3,r0,LSL #2
0001a0 f8d0f8d0 LDR r0,[r0,#0x300]
0001a4 ea32ea32 BICS r0,r2,r0
0001a8 d100 BNE |L1.428|
;;;361 {
;;;362 activeirqstatus = SET;
0001aa 2101 MOVS r1,#1
|L1.428|
;;;363 }
;;;364 else
;;;365 {
;;;366 activeirqstatus = RESET;
;;;367 }
;;;368 return activeirqstatus;
0001ac 4608 MOV r0,r1
;;;369 }
0001ae 4770 BX lr
;;;370
ENDP
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