📄 stm32f10x_adc.txt
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;;;860 }
00026a 4770 BX lr
|L1.620|
00026c 6881 LDR r1,[r0,#8]
00026e f421f421 BIC r1,r1,#0x208000
000272 6081 STR r1,[r0,#8]
000274 4770 BX lr
;;;861
ENDP
ADC_GetSoftwareStartInjectedConvCmdStatus PROC
;;;869 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
;;;870 {
000276 4601 MOV r1,r0
;;;871 FlagStatus bitstatus = RESET;
000278 2000 MOVS r0,#0
;;;872
;;;873 /* Check the status of JSWSTRT bit */
;;;874 if ((ADCx->CR2 & CR2_JSWSTRT_Set) != (u32)RESET)
00027a 6889 LDR r1,[r1,#8]
00027c f411f411 TST r1,#0x200000
000280 d000 BEQ |L1.644|
;;;875 {
;;;876 /* JSWSTRT bit is set */
;;;877 bitstatus = SET;
000282 2001 MOVS r0,#1
|L1.644|
;;;878 }
;;;879 else
;;;880 {
;;;881 /* JSWSTRT bit is reset */
;;;882 bitstatus = RESET;
;;;883 }
;;;884 /* Return the JSWSTRT bit status */
;;;885 return bitstatus;
;;;886 }
000284 4770 BX lr
;;;887
ENDP
ADC_InjectedChannelConfig PROC
;;;929 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
;;;930 {
000286 b430 PUSH {r4,r5}
;;;931 u32 tmpreg1 = 0, tmpreg2 = 0;
;;;932 u8 tmpreg3 = 0;
;;;933
;;;934 /* Check the parameters */
;;;935 assert(IS_ADC_CHANNEL(ADC_Channel));
;;;936 assert(IS_ADC_INJECTED_RANK(Rank));
;;;937 assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
;;;938
;;;939 /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
;;;940 if (ADC_Channel > ADC_Channel_9)
000288 2507 MOVS r5,#7
00028a 2909 CMP r1,#9
00028c d90c BLS |L1.680|
;;;941 {
;;;942 /* Get the old register value */
;;;943 tmpreg1 = ADCx->SMPR1;
00028e 68c4 LDR r4,[r0,#0xc]
;;;944 /* Calculate the mask to clear */
;;;945 tmpreg2 = (u32)SMPR1_SMP_Set << (3*(ADC_Channel - 10));
000290 f1a1f1a1 SUB r12,r1,#0xa
000294 eb0ceb0c ADD r12,r12,r12,LSL #1
000298 fa05fa05 LSL r5,r5,r12
;;;946 /* Clear the old discontinuous mode channel count */
;;;947 tmpreg1 &= ~tmpreg2;
00029c 43ac BICS r4,r4,r5
;;;948 /* Calculate the mask to set */
;;;949 tmpreg2 = (u32)ADC_SampleTime << (3*(ADC_Channel - 10));
00029e fa03fa03 LSL r3,r3,r12
;;;950 /* Set the discontinuous mode channel count */
;;;951 tmpreg1 |= tmpreg2;
0002a2 4323 ORRS r3,r3,r4
;;;952 /* Store the new register value */
;;;953 ADCx->SMPR1 = tmpreg1;
0002a4 60c3 STR r3,[r0,#0xc]
0002a6 e009 B |L1.700|
|L1.680|
;;;954 }
;;;955 else /* ADC_Channel include in ADC_Channel_[0..9] */
;;;956 {
;;;957 /* Get the old register value */
;;;958 tmpreg1 = ADCx->SMPR2;
0002a8 6904 LDR r4,[r0,#0x10]
;;;959 /* Calculate the mask to clear */
;;;960 tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel);
0002aa eb01eb01 ADD r12,r1,r1,LSL #1
0002ae fa05fa05 LSL r5,r5,r12
;;;961 /* Clear the old discontinuous mode channel count */
;;;962 tmpreg1 &= ~tmpreg2;
0002b2 43ac BICS r4,r4,r5
;;;963 /* Calculate the mask to set */
;;;964 tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
0002b4 fa03fa03 LSL r3,r3,r12
;;;965 /* Set the discontinuous mode channel count */
;;;966 tmpreg1 |= tmpreg2;
0002b8 4323 ORRS r3,r3,r4
;;;967 /* Store the new register value */
;;;968 ADCx->SMPR2 = tmpreg1;
0002ba 6103 STR r3,[r0,#0x10]
|L1.700|
;;;969 }
;;;970
;;;971 /* Rank configuration */
;;;972 /* Get the old register value */
;;;973 tmpreg1 = ADCx->JSQR;
0002bc 6b83 LDR r3,[r0,#0x38]
;;;974 /* Get JL value: Number = JL+1 */
;;;975 tmpreg3 = (u8)((tmpreg1 & (u32)~JSQR_JL_Reset)>> 20);
0002be f3c3f3c3 UBFX r12,r3,#20,#2
;;;976 /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
;;;977 tmpreg2 = (u32)JSQR_JSQ_Set << (5 * ((Rank + 3) - (tmpreg3 + 1)));
0002c2 eba2eba2 SUB r2,r2,r12
0002c6 1c92 ADDS r2,r2,#2
0002c8 eb02eb02 ADD r2,r2,r2,LSL #2
0002cc f04ff04f MOV r12,#0x1f
0002d0 fa0cfa0c LSL r12,r12,r2
;;;978 /* Clear the old JSQx bits for the selected rank */
;;;979 tmpreg1 &= ~tmpreg2;
0002d4 ea23ea23 BIC r3,r3,r12
;;;980 /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
;;;981 tmpreg2 = (u32)ADC_Channel << (5 * ((Rank + 3) - (tmpreg3 + 1)));
0002d8 4091 LSLS r1,r1,r2
;;;982 /* Set the JSQx bits for the selected rank */
;;;983 tmpreg1 |= tmpreg2;
0002da 4319 ORRS r1,r1,r3
;;;984 /* Store the new register value */
;;;985 ADCx->JSQR = tmpreg1;
0002dc 6381 STR r1,[r0,#0x38]
;;;986 }
0002de bc30 POP {r4,r5}
0002e0 4770 BX lr
;;;987
ENDP
ADC_InjectedSequencerLengthConfig PROC
;;;1005 /* Get the old register value */
;;;1006 tmpreg1 = ADCx->JSQR;
0002e2 6b82 LDR r2,[r0,#0x38]
;;;1007 /* Clear the old injected sequnence lenght JL bits */
;;;1008 tmpreg1 &= JSQR_JL_Reset;
0002e4 f422f422 BIC r2,r2,#0x300000
;;;1009 /* Set the injected sequnence lenght JL bits */
;;;1010 tmpreg2 = Length - 1;
0002e8 1e49 SUBS r1,r1,#1
0002ea b2c9 UXTB r1,r1
;;;1011 tmpreg1 |= (u32)tmpreg2 << 20;
0002ec ea42ea42 ORR r1,r2,r1,LSL #20
;;;1012 /* Store the new register value */
;;;1013 ADCx->JSQR = tmpreg1;
0002f0 6381 STR r1,[r0,#0x38]
;;;1014 }
0002f2 4770 BX lr
;;;1015
ENDP
ADC_SetInjectedOffset PROC
;;;1038 /* Set the selected injected channel data offset */
;;;1039 *((u32 *)((*(u32*)&ADCx) + ADC_InjectedChannel)) = (u32)Offset;
0002f4 5042 STR r2,[r0,r1]
;;;1040 }
0002f6 4770 BX lr
;;;1041
ENDP
ADC_GetInjectedConversionValue PROC
;;;1060 /* Returns the selected injected channel conversion data value */
;;;1061 return (u16) (*(u32*) (((*(u32*)&ADCx) + ADC_InjectedChannel + JDR_Offset)));
0002f8 4408 ADD r0,r0,r1
0002fa 6a80 LDR r0,[r0,#0x28]
0002fc b280 UXTH r0,r0
;;;1062 }
0002fe 4770 BX lr
;;;1063
ENDP
ADC_AnalogWatchdogCmd PROC
;;;1095 /* Get the old register value */
;;;1096 tmpreg = ADCx->CR1;
000300 6842 LDR r2,[r0,#4]
;;;1097 /* Clear AWDEN, AWDENJ and AWDSGL bits */
;;;1098 tmpreg &= CR1_AWDMode_Reset;
000302 f422f422 BIC r2,r2,#0x200
000306 f422f422 BIC r2,r2,#0xc00000
;;;1099 /* Set the analog watchdog enable mode */
;;;1100 tmpreg |= ADC_AnalogWatchdog;
00030a 4311 ORRS r1,r1,r2
;;;1101 /* Store the new register value */
;;;1102 ADCx->CR1 = tmpreg;
00030c 6041 STR r1,[r0,#4]
;;;1103 }
00030e 4770 BX lr
;;;1104
ENDP
ADC_AnalogWatchdogThresholdsConfig PROC
;;;1123 /* Set the ADCx high threshold */
;;;1124 ADCx->HTR = HighThreshold;
000310 6241 STR r1,[r0,#0x24]
;;;1125 /* Set the ADCx low threshold */
;;;1126 ADCx->LTR = LowThreshold;
000312 6282 STR r2,[r0,#0x28]
;;;1127 }
000314 4770 BX lr
;;;1128
ENDP
ADC_AnalogWatchdogSingleChannelConfig PROC
;;;1164 /* Get the old register value */
;;;1165 tmpreg = ADCx->CR1;
000316 6842 LDR r2,[r0,#4]
;;;1166 /* Clear the Analog watchdog channel select bits */
;;;1167 tmpreg &= CR1_AWDCH_Reset;
000318 f022f022 BIC r2,r2,#0x1f
;;;1168 /* Set the Analog watchdog channel */
;;;1169 tmpreg |= ADC_Channel;
00031c 4311 ORRS r1,r1,r2
;;;1170 /* Store the new register value */
;;;1171 ADCx->CR1 = tmpreg;
00031e 6041 STR r1,[r0,#4]
;;;1172 }
000320 4770 BX lr
;;;1173
ENDP
ADC_TempSensorVrefintCmd PROC
;;;1186
;;;1187 if (NewState != DISABLE)
000322 491a LDR r1,|L1.908|
000324 b130 CBZ r0,|L1.820|
;;;1188 {
;;;1189 /* Enable the temperature sensor and Vrefint channel*/
;;;1190 ADC1->CR2 |= CR2_TSVREFE_Set;
000326 f8d1f8d1 LDR r0,[r1,#0x408]
00032a f440f440 ORR r0,r0,#0x800000
00032e f8c1f8c1 STR r0,[r1,#0x408]
;;;1191 }
;;;1192 else
;;;1193 {
;;;1194 /* Disable the temperature sensor and Vrefint channel*/
;;;1195 ADC1->CR2 &= CR2_TSVREFE_Reset;
;;;1196 }
;;;1197 }
000332 4770 BX lr
|L1.820|
000334 f8d1f8d1 LDR r0,[r1,#0x408]
000338 f420f420 BIC r0,r0,#0x800000
00033c f8c1f8c1 STR r0,[r1,#0x408]
000340 4770 BX lr
;;;1198
ENDP
ADC_GetFlagStatus PROC
;;;1213 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG)
;;;1214 {
000342 4602 MOV r2,r0
;;;1215 FlagStatus bitstatus = RESET;
000344 2000 MOVS r0,#0
;;;1216
;;;1217 /* Check the parameters */
;;;1218 assert(IS_ADC_GET_FLAG(ADC_FLAG));
;;;1219
;;;1220 /* Check the status of the specified ADC flag */
;;;1221 if ((ADCx->SR & ADC_FLAG) != (u8)RESET)
000346 6812 LDR r2,[r2,#0]
000348 420a TST r2,r1
00034a d000 BEQ |L1.846|
;;;1222 {
;;;1223 /* ADC_FLAG is set */
;;;1224 bitstatus = SET;
00034c 2001 MOVS r0,#1
|L1.846|
;;;1225 }
;;;1226 else
;;;1227 {
;;;1228 /* ADC_FLAG is reset */
;;;1229 bitstatus = RESET;
;;;1230 }
;;;1231 /* Return the ADC_FLAG status */
;;;1232 return bitstatus;
;;;1233 }
00034e 4770 BX lr
;;;1234
ENDP
ADC_ClearFlag PROC
;;;1254 /* Clear the selected ADC flags */
;;;1255 ADCx->SR &= ~(u32)ADC_FLAG;
000350 6802 LDR r2,[r0,#0]
000352 ea22ea22 BIC r1,r2,r1
000356 6001 STR r1,[r0,#0]
;;;1256 }
000358 4770 BX lr
;;;1257
ENDP
ADC_GetITStatus PROC
;;;1271 {
;;;1272 ITStatus bitstatus = RESET;
00035a 2200 MOVS r2,#0
;;;1273 u8 itmask = 0, enablestatus;
;;;1274
;;;1275 /* Check the parameters */
;;;1276 assert(IS_ADC_GET_IT(ADC_IT));
;;;1277
;;;1278 /* Get the ADC IT index */
;;;1279 itmask = (u8)(ADC_IT >> 8);
00035c 0a0b LSRS r3,r1,#8
;;;1280
;;;1281 /* Get the ADC_IT enable bit status */
;;;1282 enablestatus = (ADCx->CR1 & (u8)ADC_IT) ;
00035e f8d0f8d0 LDR r12,[r0,#4]
000362 b2c9 UXTB r1,r1
000364 ea0cea0c AND r1,r12,r1
;;;1283
;;;1284 /* Check the status of the specified ADC interrupt */
;;;1285 if (((ADCx->SR & itmask) != (u8)RESET) && enablestatus)
000368 6800 LDR r0,[r0,#0]
00036a 4218 TST r0,r3
00036c d001 BEQ |L1.882|
00036e b101 CBZ r1,|L1.882|
;;;1286 {
;;;1287 /* ADC_IT is set */
;;;1288 bitstatus = SET;
000370 2201 MOVS r2,#1
|L1.882|
;;;1289 }
;;;1290 else
;;;1291 {
;;;1292 /* ADC_IT is reset */
;;;1293 bitstatus = RESET;
;;;1294 }
;;;1295 /* Return the ADC_IT status */
;;;1296 return bitstatus;
000372 4610 MOV r0,r2
;;;1297 }
000374 4770 BX lr
;;;1298
ENDP
ADC_ClearITPendingBit PROC
;;;1317 /* Get the ADC IT index */
;;;1318 itmask = (u8)(ADC_IT >> 8);
000376 0a09 LSRS r1,r1,#8
;;;1319
;;;1320 /* Clear the selected ADC interrupt pending bits */
;;;1321 ADCx->SR &= ~(u32)itmask;
000378 6802 LDR r2,[r0,#0]
00037a ea22ea22 BIC r1,r2,r1
00037e 6001 STR r1,[r0,#0]
;;;1322 }
000380 4770 BX lr
;;;1323
ENDP
000382 0000 DCW 0x0000
|L1.900|
000384 fff1f7fd DCD 0xfff1f7fd
|L1.904|
000388 4001244c DCD 0x4001244c
|L1.908|
00038c 40012000 DCD 0x40012000
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