📄 stm32f10x_can.txt
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;;;716 bitstatus = SET;
0004f6 2001 MOVS r0,#1
|L1.1272|
;;;717 }
;;;718 else
;;;719 {
;;;720 /* CAN_FLAG is reset */
;;;721 bitstatus = RESET;
;;;722 }
;;;723 /* Return the CAN_FLAG status */
;;;724 return bitstatus;
;;;725 }
0004f8 4770 BX lr
;;;726
ENDP
CAN_ClearFlag PROC
;;;739 /* Clear the selected CAN flags */
;;;740 CAN->ESR &= ~CAN_FLAG;
0004fa 495f LDR r1,|L1.1656|
0004fc 680a LDR r2,[r1,#0]
0004fe ea22ea22 BIC r0,r2,r0
000502 6008 STR r0,[r1,#0]
;;;741 }
000504 4770 BX lr
;;;742
ENDP
CheckITStatus PROC
;;;873 static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit)
;;;874 {
000506 4602 MOV r2,r0
;;;875 ITStatus pendingbitstatus = RESET;
000508 2000 MOVS r0,#0
;;;876
;;;877 if ((CAN_Reg & It_Bit) != (u32)RESET)
00050a 420a TST r2,r1
00050c d000 BEQ |L1.1296|
;;;878 {
;;;879 /* CAN_IT is set */
;;;880 pendingbitstatus = SET;
00050e 2001 MOVS r0,#1
|L1.1296|
;;;881 }
;;;882 else
;;;883 {
;;;884 /* CAN_IT is reset */
;;;885 pendingbitstatus = RESET;
;;;886 }
;;;887
;;;888 return pendingbitstatus;
;;;889 }
000510 4770 BX lr
;;;890
ENDP
CAN_GetITStatus PROC
;;;755 ITStatus CAN_GetITStatus(u32 CAN_IT)
;;;756 {
000512 4601 MOV r1,r0
;;;757 ITStatus pendingbitstatus = RESET;
000514 2000 MOVS r0,#0
;;;758
;;;759 /* Check the parameters */
;;;760 assert(IS_CAN_ITStatus(CAN_IT));
;;;761
;;;762 switch (CAN_IT)
000516 4a56 LDR r2,|L1.1648|
000518 2940 CMP r1,#0x40
00051a d03f BEQ |L1.1436|
00051c dc15 BGT |L1.1354|
00051e 2907 CMP r1,#7
000520 d02f BEQ |L1.1410|
000522 dc0a BGT |L1.1338|
000524 2904 CMP r1,#4
000526 d031 BEQ |L1.1420|
000528 2905 CMP r1,#5
00052a d026 BEQ |L1.1402|
00052c 2906 CMP r1,#6
00052e d145 BNE |L1.1468|
000530 f8d2f8d2 LDR r0,[r2,#0x408]
000534 f44ff44f MOV r1,#0x100
;;;763 {
;;;764 case CAN_IT_RQCP0:
;;;765 pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP0);
;;;766 break;
;;;767 case CAN_IT_RQCP1:
;;;768 pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP1);
000538 e7fe B CheckITStatus
|L1.1338|
00053a 2908 CMP r1,#8
00053c d02a BEQ |L1.1428|
00053e 2920 CMP r1,#0x20
000540 d13c BNE |L1.1468|
000542 f8d2f8d2 LDR r0,[r2,#0x410]
000546 2108 MOVS r1,#8
;;;769 break;
;;;770 case CAN_IT_RQCP2:
;;;771 pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP2);
;;;772 break;
;;;773 case CAN_IT_FF0:
;;;774 pendingbitstatus = CheckITStatus(CAN->RF0R, CAN_RF0R_FULL0);
;;;775 break;
;;;776 case CAN_IT_FOV0:
;;;777 pendingbitstatus = CheckITStatus(CAN->RF0R, CAN_RF0R_FOVR0);
;;;778 break;
;;;779 case CAN_IT_FF1:
;;;780 pendingbitstatus = CheckITStatus(CAN->RF1R, CAN_RF1R_FULL1);
000548 e7fe B CheckITStatus
|L1.1354|
00054a f5b1f5b1 CMP r1,#0x400
00054e d02d BEQ |L1.1452|
000550 dc09 BGT |L1.1382|
000552 f5b1f5b1 CMP r1,#0x100
000556 d025 BEQ |L1.1444|
000558 f5b1f5b1 CMP r1,#0x200
00055c d12e BNE |L1.1468|
00055e f8d2f8d2 LDR r0,[r2,#0x418]
000562 2102 MOVS r1,#2
;;;781 break;
;;;782 case CAN_IT_FOV1:
;;;783 pendingbitstatus = CheckITStatus(CAN->RF1R, CAN_RF1R_FOVR1);
;;;784 break;
;;;785 case CAN_IT_EWG:
;;;786 pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_EWGF);
;;;787 break;
;;;788 case CAN_IT_EPV:
;;;789 pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_EPVF);
000564 e7fe B CheckITStatus
|L1.1382|
000566 f5b1f5b1 CMP r1,#0x10000
00056a d023 BEQ |L1.1460|
00056c f5b1f5b1 CMP r1,#0x20000
000570 d124 BNE |L1.1468|
000572 f8d2f8d2 LDR r0,[r2,#0x404]
000576 2110 MOVS r1,#0x10
;;;790 break;
;;;791 case CAN_IT_BOF:
;;;792 pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_BOFF);
;;;793 break;
;;;794 case CAN_IT_SLK:
;;;795 pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_SLAKI);
000578 e7fe B CheckITStatus
|L1.1402|
00057a f8d2f8d2 LDR r0,[r2,#0x408]
00057e 2101 MOVS r1,#1
000580 e7fe B CheckITStatus
|L1.1410|
000582 f8d2f8d2 LDR r0,[r2,#0x408]
000586 f44ff44f MOV r1,#0x10000
00058a e7fe B CheckITStatus
|L1.1420|
00058c f8d2f8d2 LDR r0,[r2,#0x40c]
000590 2108 MOVS r1,#8
000592 e7fe B CheckITStatus
|L1.1428|
000594 f8d2f8d2 LDR r0,[r2,#0x40c]
000598 2110 MOVS r1,#0x10
00059a e7fe B CheckITStatus
|L1.1436|
00059c f8d2f8d2 LDR r0,[r2,#0x410]
0005a0 2110 MOVS r1,#0x10
0005a2 e7fe B CheckITStatus
|L1.1444|
0005a4 f8d2f8d2 LDR r0,[r2,#0x418]
0005a8 2101 MOVS r1,#1
0005aa e7fe B CheckITStatus
|L1.1452|
0005ac f8d2f8d2 LDR r0,[r2,#0x418]
0005b0 2104 MOVS r1,#4
0005b2 e7fe B CheckITStatus
|L1.1460|
;;;796 break;
;;;797 case CAN_IT_WKU:
;;;798 pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_WKUI);
0005b4 f8d2f8d2 LDR r0,[r2,#0x404]
0005b8 2108 MOVS r1,#8
0005ba e7fe B CheckITStatus
|L1.1468|
;;;799 break;
;;;800
;;;801 default :
;;;802 pendingbitstatus = RESET;
;;;803 break;
;;;804 }
;;;805
;;;806 /* Return the CAN_IT status */
;;;807 return pendingbitstatus;
;;;808 }
0005bc 4770 BX lr
;;;809
ENDP
CAN_ClearITPendingBit PROC
;;;821
;;;822 switch (CAN_IT)
0005be 492c LDR r1,|L1.1648|
0005c0 2208 MOVS r2,#8
0005c2 2310 MOVS r3,#0x10
0005c4 2840 CMP r0,#0x40
0005c6 d03e BEQ |L1.1606|
0005c8 dc14 BGT |L1.1524|
0005ca 2807 CMP r0,#7
0005cc d030 BEQ |L1.1584|
0005ce dc0a BGT |L1.1510|
0005d0 2804 CMP r0,#4
0005d2 d032 BEQ |L1.1594|
0005d4 2805 CMP r0,#5
0005d6 d027 BEQ |L1.1576|
0005d8 2806 CMP r0,#6
0005da d103 BNE |L1.1508|
;;;823 {
;;;824 case CAN_IT_RQCP0:
;;;825 CAN->TSR = CAN_TSR_RQCP0; /* rc_w1*/
;;;826 break;
;;;827 case CAN_IT_RQCP1:
;;;828 CAN->TSR = CAN_TSR_RQCP1; /* rc_w1*/
0005dc f44ff44f MOV r0,#0x100
0005e0 f8c1f8c1 STR r0,[r1,#0x408]
|L1.1508|
;;;829 break;
;;;830 case CAN_IT_RQCP2:
;;;831 CAN->TSR = CAN_TSR_RQCP2; /* rc_w1*/
;;;832 break;
;;;833 case CAN_IT_FF0:
;;;834 CAN->RF0R = CAN_RF0R_FULL0; /* rc_w1*/
;;;835 break;
;;;836 case CAN_IT_FOV0:
;;;837 CAN->RF0R = CAN_RF0R_FOVR0; /* rc_w1*/
;;;838 break;
;;;839 case CAN_IT_FF1:
;;;840 CAN->RF1R = CAN_RF1R_FULL1; /* rc_w1*/
;;;841 break;
;;;842 case CAN_IT_FOV1:
;;;843 CAN->RF1R = CAN_RF1R_FOVR1; /* rc_w1*/
;;;844 break;
;;;845 case CAN_IT_EWG:
;;;846 CAN->ESR &= ~ CAN_ESR_EWGF; /* rw */
;;;847 break;
;;;848 case CAN_IT_EPV:
;;;849 CAN->ESR &= ~ CAN_ESR_EPVF; /* rw */
;;;850 break;
;;;851 case CAN_IT_BOF:
;;;852 CAN->ESR &= ~ CAN_ESR_BOFF; /* rw */
;;;853 break;
;;;854 case CAN_IT_WKU:
;;;855 CAN->MSR = CAN_MSR_WKUI; /* rc_w1*/
;;;856 break;
;;;857 case CAN_IT_SLK:
;;;858 CAN->MSR = CAN_MSR_SLAKI; /* rc_w1*/
;;;859 break;
;;;860 default :
;;;861 break;
;;;862 }
;;;863 }
0005e4 4770 BX lr
|L1.1510|
0005e6 2808 CMP r0,#8
0005e8 d02a BEQ |L1.1600|
0005ea 2820 CMP r0,#0x20
0005ec d1fa BNE |L1.1508|
0005ee f8c1f8c1 STR r2,[r1,#0x410]
|L1.1522|
0005f2 4770 BX lr
|L1.1524|
0005f4 f5b0f5b0 CMP r0,#0x400
0005f8 d02f BEQ |L1.1626|
0005fa dc0c BGT |L1.1558|
0005fc f5b0f5b0 CMP r0,#0x100
000600 d024 BEQ |L1.1612|
000602 f5b0f5b0 CMP r0,#0x200
000606 d1f4 BNE |L1.1522|
000608 f8d1f8d1 LDR r0,[r1,#0x418]
00060c f020f020 BIC r0,r0,#2
000610 f8c1f8c1 STR r0,[r1,#0x418]
|L1.1556|
000614 4770 BX lr
|L1.1558|
000616 f5b0f5b0 CMP r0,#0x10000
00061a d025 BEQ |L1.1640|
00061c f5b0f5b0 CMP r0,#0x20000
000620 d1f8 BNE |L1.1556|
000622 f8c1f8c1 STR r3,[r1,#0x404]
000626 4770 BX lr
|L1.1576|
000628 2001 MOVS r0,#1
00062a f8c1f8c1 STR r0,[r1,#0x408]
00062e 4770 BX lr
|L1.1584|
000630 f44ff44f MOV r0,#0x10000
000634 f8c1f8c1 STR r0,[r1,#0x408]
000638 4770 BX lr
|L1.1594|
00063a f8c1f8c1 STR r2,[r1,#0x40c]
00063e 4770 BX lr
|L1.1600|
000640 f8c1f8c1 STR r3,[r1,#0x40c]
000644 4770 BX lr
|L1.1606|
000646 f8c1f8c1 STR r3,[r1,#0x410]
00064a 4770 BX lr
|L1.1612|
00064c f8d1f8d1 LDR r0,[r1,#0x418]
000650 f020f020 BIC r0,r0,#1
000654 f8c1f8c1 STR r0,[r1,#0x418]
000658 4770 BX lr
|L1.1626|
00065a f8d1f8d1 LDR r0,[r1,#0x418]
00065e f020f020 BIC r0,r0,#4
000662 f8c1f8c1 STR r0,[r1,#0x418]
000666 4770 BX lr
|L1.1640|
000668 f8c1f8c1 STR r2,[r1,#0x404]
00066c 4770 BX lr
;;;864
ENDP
00066e 0000 DCW 0x0000
|L1.1648|
000670 40006000 DCD 0x40006000
|L1.1652|
000674 40006400 DCD 0x40006400
|L1.1656|
000678 40006418 DCD 0x40006418
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