📄 fxemu2c.asm
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;Copyright (C) 1997-2007 ZSNES Team ( zsKnight, _Demo_, pagefault, Nach );;http://www.zsnes.com;http://sourceforge.net/projects/zsnes;https://zsnes.bountysource.com;;This program is free software; you can redistribute it and/or;modify it under the terms of the GNU General Public License;version 2 as published by the Free Software Foundation.;;This program is distributed in the hope that it will be useful,;but WITHOUT ANY WARRANTY; without even the implied warranty of;MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the;GNU General Public License for more details.;;You should have received a copy of the GNU General Public License;along with this program; if not, write to the Free Software;Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.%include "macros.mac"EXTSYM FXEndLoop,FlushCache,FxOp02,FxTable,FxTableb,FxTablec,FxTabledEXTSYM NumberOfOpcodes,SfxB,SfxCBR,SfxCFGR,SfxCOLR,SfxCPB,SfxCROMEXTSYM SfxCacheActive,SfxCarry,SfxLastRamAdr,SfxMemTable,SfxOverflowEXTSYM SfxPBR,SfxPIPE,SfxPOR,SfxR0,SfxR1,SfxR11,SfxR12,SfxR13,SfxR14EXTSYM SfxR15,SfxR2,SfxR4,SfxR6,SfxR7,SfxR8,SfxRAMBR,SfxRAMMem,SfxROMBREXTSYM SfxRomBuffer,SfxSCBR,SfxSCMR,SfxSFR,SfxSignZero,SfxnRamBanks,flagnzEXTSYM sfx128lineloc,sfx160lineloc,sfx192lineloc,sfxobjlineloc,sfxramdataEXTSYM withr15sk,sfxclineloc,SCBRrel,ChangeOpsEXTSYM fxbit01pcal,fxbit23pcal,fxbit45pcal,fxbit67pcalEXTSYM fxbit01,fxbit23,fxbit45,fxbit67,fxxand,PLOTJmpa,PLOTJmpb%include "chips/fxemu2.mac"%include "chips/fxemu2c.mac"SECTION .textALIGN32NEWSYM FxOpd00 ; STOP stop GSU execution (and maybe generate an IRQ) ; Verified. FETCHPIPE mov [SfxPIPE],cl and dword[SfxSFR],0FFFFh-32 ; Clear Go flag (set to 1 when the GSU is running) test dword[SfxCFGR],080h ; Check if the interrupt generation is on jnz .NoIRQ ; Set IRQ Flag.NoIRQ CLRFLAGS inc ebp mov eax,[NumberOfOpcodes] add eax,0F0000000h add [ChangeOps],eax mov dword[NumberOfOpcodes],1 jmp FXEndLoop FXReturnNEWSYM FxOpd01 ; NOP no operation ; Verified. FETCHPIPE CLRFLAGS inc ebp ; Increase program counter FXReturnNEWSYM FxOpd02 ; CACHE reintialize GSU cache mov eax,ebp FETCHPIPE sub eax,[SfxCPB] and eax,0FFF0h cmp dword[SfxCBR],eax je .SkipUpdate cmp byte[SfxCacheActive],1 je .SkipUpdate mov [SfxCBR],eax mov dword[SfxCacheActive],1 call FlushCache.SkipUpdate CLRFLAGS inc ebp ; Increase program counter FXReturnNEWSYM FxOpd03 ; LSR logic shift right ; Verified. mov eax,[esi] ; Read Source FETCHPIPE mov [SfxCarry],al and byte[SfxCarry],1 shr ax,1 ; logic shift right inc ebp ; Increase program counter mov [edi],eax ; Write Destination mov [SfxSignZero],eax CLRFLAGS FXReturnNEWSYM FxOpd04 ; ROL rotate left (RCL?) ; V shr byte[SfxCarry],1 mov eax,[esi] ; Read Source FETCHPIPE rcl ax,1 rcl byte[SfxCarry],1 inc ebp ; Increase program counter mov [edi],eax ; Write Destination mov [SfxSignZero],eax CLRFLAGS FXReturnNEWSYM FxOpd05 ; BRA branch always ; Verified. movsx eax,byte[ebp] mov cl,[ebp+1] inc ebp add ebp,eax call [FxTable+ecx*4] FXReturn2NEWSYM FxOpd06 ; BGE branch on greater or equals ; Verified. movsx eax,byte[ebp] mov ebx,[SfxSignZero] shr ebx,15 inc ebp xor bl,[SfxOverflow] mov cl,[ebp] test bl,01h jnz .nojump add ebp,eax call [FxTable+ecx*4] FXReturn2.nojump inc ebp call [FxTable+ecx*4] FXReturn2NEWSYM FxOpd07 ; BLT branch on lesss than ; Verified. movsx eax,byte[ebp] mov ebx,[SfxSignZero] shr ebx,15 inc ebp xor bl,[SfxOverflow] mov cl,[ebp] test bl,01h jz .nojump add ebp,eax call [FxTable+ecx*4] FXReturn2.nojump inc ebp call [FxTable+ecx*4] FXReturn2NEWSYM FxOpd08 ; BNE branch on not equal ; Verified. movsx eax,byte[ebp] inc ebp test dword[SfxSignZero],0FFFFh mov cl,[ebp] jz .nojump add ebp,eax call [FxTable+ecx*4] FXReturn2.nojump inc ebp call [FxTable+ecx*4] FXReturn2NEWSYM FxOpd09 ; BEQ branch on equal (z=1) ; Verified. movsx eax,byte[ebp] inc ebp test dword[SfxSignZero],0FFFFh mov cl,[ebp] jnz .nojump add ebp,eax call [FxTable+ecx*4] FXReturn2.nojump inc ebp call [FxTable+ecx*4] FXReturn2NEWSYM FxOpd0A ; BPL branch on plus ; Verified. movsx eax,byte[ebp] inc ebp test dword[SfxSignZero],088000h mov cl,[ebp] jnz .nojump add ebp,eax call [FxTable+ecx*4] FXReturn2.nojump inc ebp call [FxTable+ecx*4] FXReturn2NEWSYM FxOpd0B ; BMI branch on minus ; Verified. movsx eax,byte[ebp] inc ebp test dword[SfxSignZero],088000h mov cl,[ebp] jz .nojump add ebp,eax call [FxTable+ecx*4] FXReturn2.nojump inc ebp call [FxTable+ecx*4] FXReturn2NEWSYM FxOpd0C ; BCC branch on carry clear ; Verified. movsx eax,byte[ebp] inc ebp test byte[SfxCarry],01h mov cl,[ebp] jnz .nojump add ebp,eax call [FxTable+ecx*4] FXReturn2.nojump inc ebp call [FxTable+ecx*4] FXReturn2NEWSYM FxOpd0D ; BCS branch on carry set ; Verified. movsx eax,byte[ebp] inc ebp test byte[SfxCarry],01h mov cl,[ebp] jz .nojump add ebp,eax call [FxTable+ecx*4] FXReturn2.nojump inc ebp call [FxTable+ecx*4] FXReturn2NEWSYM FxOpd0E ; BVC branch on overflow clear ; Verified. movsx eax,byte[ebp] inc ebp test byte[SfxOverflow],01h mov cl,[ebp] jnz .nojump add ebp,eax call [FxTable+ecx*4] FXReturn2.nojump inc ebp call [FxTable+ecx*4] FXReturn2NEWSYM FxOpd0F ; BVS branch on overflow set ; Verified. movsx eax,byte[ebp] inc ebp test byte[SfxOverflow],01h mov cl,[ebp] jz .nojump add ebp,eax call [FxTable+ecx*4] FXReturn2.nojump inc ebp call [FxTable+ecx*4] FXReturn2NEWSYM FxOpd10 ; TO RN set register n as destination register TORNd 0NEWSYM FxOpd11 ; TO RN set register n as destination register TORNd 1NEWSYM FxOpd12 ; TO RN set register n as destination register TORNd 2NEWSYM FxOpd13 ; TO RN set register n as destination register TORNd 3NEWSYM FxOpd14 ; TO RN set register n as destination register TORNd 4NEWSYM FxOpd15 ; TO RN set register n as destination register TORNd 5NEWSYM FxOpd16 ; TO RN set register n as destination register TORNd 6NEWSYM FxOpd17 ; TO RN set register n as destination register TORNd 7NEWSYM FxOpd18 ; TO RN set register n as destination register TORNd 8NEWSYM FxOpd19 ; TO RN set register n as destination register TORNd 9NEWSYM FxOpd1A ; TO RN set register n as destination register TORNd 10NEWSYM FxOpd1B ; TO RN set register n as destination register TORNd 11NEWSYM FxOpd1C ; TO RN set register n as destination register TORNd 12NEWSYM FxOpd1D ; TO RN set register n as destination register TORNd 13NEWSYM FxOpd1E ; TO RN set register n as destination register FETCHPIPE mov edi,SfxR0+14*4 inc ebp call [FxTable+ecx*4] mov edi,SfxR0 UpdateR14 FXReturnNEWSYM FxOpd1F ; TO RN set register n as destination register FETCHPIPE mov edi,SfxR0+15*4 inc ebp call [FxTable+ecx*4] mov ebp,[SfxCPB] add ebp,[SfxR15] mov edi,SfxR0 FXReturnNEWSYM FxOpd20 ; WITH set register n as source and destination register WITHc 0NEWSYM FxOpd21 ; WITH set register n as source and destination register WITHc 1NEWSYM FxOpd22 ; WITH set register n as source and destination register WITHc 2NEWSYM FxOpd23 ; WITH set register n as source and destination register WITHc 3NEWSYM FxOpd24 ; WITH set register n as source and destination register WITHc 4NEWSYM FxOpd25 ; WITH set register n as source and destination register WITHc 5NEWSYM FxOpd26 ; WITH set register n as source and destination register WITHc 6NEWSYM FxOpd27 ; WITH set register n as source and destination register WITHc 7NEWSYM FxOpd28 ; WITH set register n as source and destination register WITHc 8NEWSYM FxOpd29 ; WITH set register n as source and destination register WITHc 9NEWSYM FxOpd2A ; WITH set register n as source and destination register WITHc 10NEWSYM FxOpd2B ; WITH set register n as source and destination register WITHc 11NEWSYM FxOpd2C ; WITH set register n as source and destination register WITHc 12NEWSYM FxOpd2D ; WITH set register n as source and destination register WITHc 13NEWSYM FxOpd2E ; WITH set register n as source and destination register FETCHPIPE mov esi,SfxR0+14*4 mov edi,SfxR0+14*4 mov dword[SfxB],1 inc ebp call [FxTablec+ecx*4] mov dword[SfxB],0 ; Clear B Flag mov esi,SfxR0 mov edi,SfxR0 UpdateR14 FXReturnNEWSYM FxOpd2F ; WITH set register n as source and destination register FETCHPIPE mov esi,SfxR0+15*4 mov edi,SfxR0+15*4 mov dword[SfxB],1 inc ebp mov eax,ebp sub eax,[SfxCPB] mov dword[withr15sk],0 mov [SfxR15],eax call [FxTableb+ecx*4] cmp dword[withr15sk],1 je .skip mov ebp,[SfxCPB] add ebp,[SfxR15].skip mov dword[SfxB],0 ; Clear B Flag mov esi,SfxR0 mov edi,SfxR0 FXReturnNEWSYM FxOpd30 ; STW RN store word STWRNc 0NEWSYM FxOpd31 ; STW RN store word STWRNc 1NEWSYM FxOpd32 ; STW RN store word STWRNc 2NEWSYM FxOpd33 ; STW RN store word STWRNc 3NEWSYM FxOpd34 ; STW RN store word STWRNc 4NEWSYM FxOpd35 ; STW RN store word STWRNc 5NEWSYM FxOpd36 ; STW RN store word STWRNc 6NEWSYM FxOpd37 ; STW RN store word STWRNc 7NEWSYM FxOpd38 ; STW RN store word STWRNc 8NEWSYM FxOpd39 ; STW RN store word STWRNc 9NEWSYM FxOpd3A ; STW RN store word STWRNc 10NEWSYM FxOpd3B ; STW RN store word STWRNc 11NEWSYM FxOpd30A1 ; STB RN store byte STBRNc 0NEWSYM FxOpd31A1 ; STB RN store byte STBRNc 1NEWSYM FxOpd32A1 ; STB RN store byte STBRNc 2NEWSYM FxOpd33A1 ; STB RN store byte STBRNc 3NEWSYM FxOpd34A1 ; STB RN store byte STBRNc 4NEWSYM FxOpd35A1 ; STB RN store byte STBRNc 5NEWSYM FxOpd36A1 ; STB RN store byte STBRNc 6NEWSYM FxOpd37A1 ; STB RN store byte STBRNc 7NEWSYM FxOpd38A1 ; STB RN store byte STBRNc 8NEWSYM FxOpd39A1 ; STB RN store byte STBRNc 9NEWSYM FxOpd3AA1 ; STB RN store byte STBRNc 10NEWSYM FxOpd3BA1 ; STB RN store byte STBRNc 11NEWSYM FxOpd3C ; LOOP decrement loop counter, and branch on not zero ; V dec word[SfxR12] ; decrement loop counter FETCHPIPE mov eax,[SfxR12] mov [SfxSignZero],eax or eax,eax jz .NoBranch mov eax,[SfxR13] mov ebp,[SfxCPB] add ebp,eax CLRFLAGS FXReturn.NoBranch inc ebp CLRFLAGS FXReturnNEWSYM FxOpd3D ; ALT1 set alt1 mode ; Verified. FETCHPIPE mov dword[SfxB],0 or ch,01h inc ebp call [FxTable+ecx*4] xor ch,ch FXReturnNEWSYM FxOpd3E ; ALT2 set alt1 mode ; Verified. FETCHPIPE mov dword[SfxB],0 or ch,02h inc ebp call [FxTable+ecx*4] xor ch,ch FXReturnNEWSYM FxOpd3F ; ALT3 set alt3 mode ; Verified. FETCHPIPE mov dword[SfxB],0 or ch,03h inc ebp call [FxTable+ecx*4] xor ch,ch FXReturnNEWSYM FxOpd40 ; LDW RN load word from RAM LDWRNc 0NEWSYM FxOpd41 ; LDW RN load word from RAM LDWRNc 1NEWSYM FxOpd42 ; LDW RN load word from RAM LDWRNc 2NEWSYM FxOpd43 ; LDW RN load word from RAM LDWRNc 3NEWSYM FxOpd44 ; LDW RN load word from RAM LDWRNc 4NEWSYM FxOpd45 ; LDW RN load word from RAM LDWRNc 5NEWSYM FxOpd46 ; LDW RN load word from RAM LDWRNc 6NEWSYM FxOpd47 ; LDW RN load word from RAM LDWRNc 7NEWSYM FxOpd48 ; LDW RN load word from RAM LDWRNc 8
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