rei2c.hier_info

用VHDL编写的quartusii平台上的串行EEPROM配置读取的程序。

|rei2c
reset => sda~reg0.PRESET
reset => count[2].ACLR
reset => count[1].ACLR
reset => count[0].ACLR
reset => datacount[3].ACLR
reset => datacount[2].ACLR
reset => datacount[1].ACLR
reset => datacount[0].ACLR
reset => i[14].ACLR
reset => i[13].ACLR
reset => i[12].ACLR
reset => i[11].ACLR
reset => i[10].ACLR
reset => i[9].ACLR
reset => i[8].ACLR
reset => i[7].ACLR
reset => i[6].ACLR
reset => i[5].ACLR
reset => i[4].ACLR
reset => i[3].ACLR
reset => i[2].ACLR
reset => i[1].ACLR
reset => i[0].ACLR
reset => dout[7]~reg0.ACLR
reset => dout[6]~reg0.ACLR
reset => dout[5]~reg0.ACLR
reset => dout[4]~reg0.ACLR
reset => dout[3]~reg0.ACLR
reset => dout[2]~reg0.ACLR
reset => dout[1]~reg0.ACLR
reset => dout[0]~reg0.ACLR
reset => oe~reg0.ACLR
reset => process1~3.PRESET
reset => scl~reg0.ACLR
reset => i2c_active.ACLR
reset => state~238.IN1
clk => i2c_active.CLK
clk => sda~reg0.CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => datacount[3].CLK
clk => datacount[2].CLK
clk => datacount[1].CLK
clk => datacount[0].CLK
clk => i[14].CLK
clk => i[13].CLK
clk => i[12].CLK
clk => i[11].CLK
clk => i[10].CLK
clk => i[9].CLK
clk => i[8].CLK
clk => i[7].CLK
clk => i[6].CLK
clk => i[5].CLK
clk => i[4].CLK
clk => i[3].CLK
clk => i[2].CLK
clk => i[1].CLK
clk => i[0].CLK
clk => dout[7]~reg0.CLK
clk => dout[6]~reg0.CLK
clk => dout[5]~reg0.CLK
clk => dout[4]~reg0.CLK
clk => dout[3]~reg0.CLK
clk => dout[2]~reg0.CLK
clk => dout[1]~reg0.CLK
clk => dout[0]~reg0.CLK
clk => oe~reg0.CLK
clk => data[7].CLK
clk => data[6].CLK
clk => data[5].CLK
clk => data[4].CLK
clk => data[3].CLK
clk => data[2].CLK
clk => data[1].CLK
clk => data[0].CLK
clk => process1~3.CLK
clk => scl~reg0.CLK
clk => state~237.IN1
rd => datacount~10.OUTPUTSELECT
rd => datacount~11.OUTPUTSELECT
rd => datacount~12.OUTPUTSELECT
rd => datacount~13.OUTPUTSELECT
rd => state~193.OUTPUTSELECT
rd => state~194.OUTPUTSELECT
rd => state~195.OUTPUTSELECT
rd => state~196.OUTPUTSELECT
rd => state~197.OUTPUTSELECT
rd => state~198.OUTPUTSELECT
rd => state~199.OUTPUTSELECT
rd => state~200.OUTPUTSELECT
rd => state~201.OUTPUTSELECT
rd => state~202.OUTPUTSELECT
rd => state~203.OUTPUTSELECT
rd => process1~0.IN1
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oe <= oe~reg0.DB_MAX_OUTPUT_PORT_TYPE
sda <= process1~2
scl <= scl~reg0.DB_MAX_OUTPUT_PORT_TYPE