epptop.map.eqn

在altera fpga中实现epp模式的并口通信程序

--B1L02 is EPP2SRAM:M0|add~72
B1L02 = B1_sram_raddr[2] $ (B1_EPP_DataStrobe & B1_sram_raddr[1] & B1_sram_raddr[0]);


--B1L28 is EPP2SRAM:M0|sram_raddr[0]~19
B1L28 = B1_epp_state.EPP_WAIT_DATAREAD # !RST;


--B1L44 is EPP2SRAM:M0|epp_datain~74
B1L44 = A1L61 & RST;


--C1L12 is ram_dp_ar_aw:m1|data_0_out[1]~141
C1L12 = B1L01 & B1L11 # !B1L01 & B1L11 & C1_mem[4][1] # !B1L11 & C1_mem[0][1];


--C1L22 is ram_dp_ar_aw:m1|data_0_out[1]~142
C1L22 = B1L01 & C1L12 & C1_mem[6][1] # !C1L12 & C1_mem[2][1] # !B1L01 & C1L12;


--C1L32 is ram_dp_ar_aw:m1|data_0_out[1]~143
C1L32 = C1L55 & !C1L65 # !C1L55 & C1L65 & C1_mem[1][1] # !C1L65 & C1L22;


--C1L42 is ram_dp_ar_aw:m1|data_0_out[1]~144
C1L42 = C1L55 & C1L32 & C1_mem[3][1] # !C1L32 & C1_mem[5][1] # !C1L55 & C1L32;


--C1L46 is ram_dp_ar_aw:m1|data_0_out~115
C1L46 = C1L42 & !B1_cmd[0] & !B1_SRAM_CE;


--B1L22 is EPP2SRAM:M0|add~82
B1L22 = B1_sram_waddr[1] $ (B1_EPP_DataStrobe & B1_sram_waddr[0]);


--B1L91 is EPP2SRAM:M0|add~67
B1L91 = B1_sram_raddr[1] $ (B1_EPP_DataStrobe & B1_sram_raddr[0]);


--B1L54 is EPP2SRAM:M0|epp_datain~75
B1L54 = A1L41 & RST;


--C1L61 is ram_dp_ar_aw:m1|data_0_out[0]~145
C1L61 = B1L11 & B1L01 # !B1L11 & B1L01 & C1_mem[2][0] # !B1L01 & C1_mem[0][0];


--C1L71 is ram_dp_ar_aw:m1|data_0_out[0]~146
C1L71 = B1L11 & C1L61 & C1_mem[6][0] # !C1L61 & C1_mem[4][0] # !B1L11 & C1L61;


--C1L81 is ram_dp_ar_aw:m1|data_0_out[0]~147
C1L81 = C1L65 & C1L55 & C1_mem[5][0] # !C1L55 & C1_mem[1][0] # !C1L65 & C1L55;


--C1L91 is ram_dp_ar_aw:m1|data_0_out[0]~148
C1L91 = C1L65 & C1L81 # !C1L65 & C1L81 & C1_mem[3][0] # !C1L81 & C1L71;


--C1L56 is ram_dp_ar_aw:m1|data_0_out~116
C1L56 = C1L91 & !B1_cmd[0] & !B1_SRAM_CE;


--B1L12 is EPP2SRAM:M0|add~77
B1L12 = B1_EPP_DataStrobe $ B1_sram_waddr[0];


--B1L81 is EPP2SRAM:M0|add~62
B1L81 = B1_EPP_DataStrobe $ B1_sram_raddr[0];


--C1L1 is ram_dp_ar_aw:m1|always0~1
C1L1 = B1_cmd[0] & !B1_SRAM_CE;


--C1L031 is ram_dp_ar_aw:m1|mem[0]~4070
C1L031 = C1L4 & C1L1 & A1L8 # !C1L1 & A1L25;


--C1L2 is ram_dp_ar_aw:m1|always0~179
C1L2 = SRAMOE & !SRAMWE & !SRAMCS;


--C1L881 is ram_dp_ar_aw:m1|mem[5][0]~4071
C1L881 = SRAMADDR[1] # !C1L2 # !SRAMADDR[0] # !SRAMADDR[2];


--C1L75 is ram_dp_ar_aw:m1|data_0_out[7]~325
C1L75 = B1L11 & B1L9 & !B1L01;


--C1L981 is ram_dp_ar_aw:m1|mem[5][0]~4072
C1L981 = C1L1 & C1L75 # !C1L1 & !C1L881 # !C1L4;


--C1L551 is ram_dp_ar_aw:m1|mem[2][3]~4073
C1L551 = B1L11 # B1L9 # !B1L01;


--C1L651 is ram_dp_ar_aw:m1|mem[2][3]~4074
C1L651 = SRAMADDR[2] # SRAMADDR[0] # !C1L2 # !SRAMADDR[1];


--C1L751 is ram_dp_ar_aw:m1|mem[2][3]~4075
C1L751 = C1L1 & !C1L551 # !C1L1 & !C1L651 # !C1L4;


--C1L671 is ram_dp_ar_aw:m1|mem[4][0]~4076
C1L671 = B1L01 # B1L9 # !B1L11;


--C1L771 is ram_dp_ar_aw:m1|mem[4][0]~4077
C1L771 = SRAMADDR[1] # SRAMADDR[0] # !C1L2 # !SRAMADDR[2];


--C1L871 is ram_dp_ar_aw:m1|mem[4][0]~4078
C1L871 = C1L1 & !C1L671 # !C1L1 & !C1L771 # !C1L4;


--C1L521 is ram_dp_ar_aw:m1|mem[0][5]~4079
C1L521 = B1L11 # B1L01 # B1L9;


--C1L621 is ram_dp_ar_aw:m1|mem[0][5]~4080
C1L621 = SRAMADDR[2] # SRAMADDR[1] # SRAMADDR[0] # !C1L2;


--C1L721 is ram_dp_ar_aw:m1|mem[0][5]~4081
C1L721 = C1L1 & !C1L521 # !C1L1 & !C1L621 # !C1L4;


--C1L402 is ram_dp_ar_aw:m1|mem[6][5]~4082
C1L402 = B1L9 # !B1L01 # !B1L11;


--C1L502 is ram_dp_ar_aw:m1|mem[6][5]~4083
C1L502 = SRAMADDR[0] # !C1L2 # !SRAMADDR[1] # !SRAMADDR[2];


--C1L602 is ram_dp_ar_aw:m1|mem[6][5]~4084
C1L602 = C1L1 & !C1L402 # !C1L1 & !C1L502 # !C1L4;


--C1L041 is ram_dp_ar_aw:m1|mem[1][0]~4085
C1L041 = B1L11 # B1L01 # !B1L9;


--C1L141 is ram_dp_ar_aw:m1|mem[1][0]~4086
C1L141 = SRAMADDR[2] # SRAMADDR[1] # !C1L2 # !SRAMADDR[0];


--C1L241 is ram_dp_ar_aw:m1|mem[1][0]~4087
C1L241 = C1L1 & !C1L041 # !C1L1 & !C1L141 # !C1L4;


--C1L461 is ram_dp_ar_aw:m1|mem[3][0]~4088
C1L461 = B1L11 # !B1L9 # !B1L01;


--C1L561 is ram_dp_ar_aw:m1|mem[3][0]~4089
C1L561 = SRAMADDR[2] # !C1L2 # !SRAMADDR[0] # !SRAMADDR[1];


--C1L661 is ram_dp_ar_aw:m1|mem[3][0]~4090
C1L661 = C1L1 & !C1L461 # !C1L1 & !C1L561 # !C1L4;


--C1L131 is ram_dp_ar_aw:m1|mem[0]~4091
C1L131 = C1L4 & C1L1 & A1L7 # !C1L1 & A1L05;


--C1L231 is ram_dp_ar_aw:m1|mem[0]~4092
C1L231 = C1L4 & C1L1 & A1L6 # !C1L1 & A1L84;


--C1L331 is ram_dp_ar_aw:m1|mem[0]~4093
C1L331 = C1L4 & C1L1 & A1L5 # !C1L1 & A1L64;


--C1L431 is ram_dp_ar_aw:m1|mem[0]~4094
C1L431 = C1L4 & C1L1 & A1L4 # !C1L1 & A1L44;


--C1L531 is ram_dp_ar_aw:m1|mem[0]~4095
C1L531 = C1L4 & C1L1 & A1L3 # !C1L1 & A1L24;


--C1L631 is ram_dp_ar_aw:m1|mem[0]~4096
C1L631 = C1L4 & C1L1 & A1L2 # !C1L1 & A1L04;


--C1L731 is ram_dp_ar_aw:m1|mem[0]~4097
C1L731 = C1L4 & C1L1 & A1L1 # !C1L1 & A1L83;


--B1L03 is EPP2SRAM:M0|epp_datain[0]~156
B1L03 = !B1_epp_state.EPP_IDLE & !B1_EPP_Write & B1L47 # !RST;


--B1L31 is EPP2SRAM:M0|SRAM_CE~9
B1L31 = !RST;


--CLK is CLK
--operation mode is input

CLK = INPUT();


--RST is RST
--operation mode is input

RST = INPUT();


--DS is DS
--operation mode is input

DS = INPUT();


--AS is AS
--operation mode is input

AS = INPUT();


--SRAMWE is SRAMWE
--operation mode is input

SRAMWE = INPUT();


--SRAMCS is SRAMCS
--operation mode is input

SRAMCS = INPUT();


--SRAMOE is SRAMOE
--operation mode is input

SRAMOE = INPUT();


--WRITE is WRITE
--operation mode is input

WRITE = INPUT();


--SRAMADDR[0] is SRAMADDR[0]
--operation mode is input

SRAMADDR[0] = INPUT();


--SRAMADDR[2] is SRAMADDR[2]
--operation mode is input

SRAMADDR[2] = INPUT();


--SRAMADDR[1] is SRAMADDR[1]
--operation mode is input

SRAMADDR[1] = INPUT();


--INT is INT
--operation mode is output

INT = OUTPUT(GND);


--WAIT is WAIT
--operation mode is output

WAIT = OUTPUT(B1_EPP_Wait);


--A1L82 is EPPDATA[7]~0
--operation mode is bidir

A1L82 = EPPDATA[7];

--EPPDATA[7] is EPPDATA[7]
--operation mode is bidir

EPPDATA[7]_tri_out = TRI(B1_epp_dataout[7], B1L5);
EPPDATA[7] = BIDIR(EPPDATA[7]_tri_out);


--A1L62 is EPPDATA[6]~1
--operation mode is bidir

A1L62 = EPPDATA[6];

--EPPDATA[6] is EPPDATA[6]
--operation mode is bidir

EPPDATA[6]_tri_out = TRI(B1_epp_dataout[6], B1L5);
EPPDATA[6] = BIDIR(EPPDATA[6]_tri_out);


--A1L42 is EPPDATA[5]~2
--operation mode is bidir

A1L42 = EPPDATA[5];

--EPPDATA[5] is EPPDATA[5]
--operation mode is bidir

EPPDATA[5]_tri_out = TRI(B1_epp_dataout[5], B1L5);
EPPDATA[5] = BIDIR(EPPDATA[5]_tri_out);


--A1L22 is EPPDATA[4]~3
--operation mode is bidir

A1L22 = EPPDATA[4];

--EPPDATA[4] is EPPDATA[4]
--operation mode is bidir

EPPDATA[4]_tri_out = TRI(B1_epp_dataout[4], B1L5);
EPPDATA[4] = BIDIR(EPPDATA[4]_tri_out);


--A1L02 is EPPDATA[3]~4
--operation mode is bidir

A1L02 = EPPDATA[3];

--EPPDATA[3] is EPPDATA[3]
--operation mode is bidir

EPPDATA[3]_tri_out = TRI(B1_epp_dataout[3], B1L5);
EPPDATA[3] = BIDIR(EPPDATA[3]_tri_out);


--A1L81 is EPPDATA[2]~5
--operation mode is bidir

A1L81 = EPPDATA[2];

--EPPDATA[2] is EPPDATA[2]
--operation mode is bidir

EPPDATA[2]_tri_out = TRI(B1_epp_dataout[2], B1L5);
EPPDATA[2] = BIDIR(EPPDATA[2]_tri_out);


--A1L61 is EPPDATA[1]~6
--operation mode is bidir

A1L61 = EPPDATA[1];

--EPPDATA[1] is EPPDATA[1]
--operation mode is bidir

EPPDATA[1]_tri_out = TRI(B1_epp_dataout[1], B1L5);
EPPDATA[1] = BIDIR(EPPDATA[1]_tri_out);


--A1L41 is EPPDATA[0]~7
--operation mode is bidir

A1L41 = EPPDATA[0];

--EPPDATA[0] is EPPDATA[0]
--operation mode is bidir

EPPDATA[0]_tri_out = TRI(B1_epp_dataout[0], B1L5);
EPPDATA[0] = BIDIR(EPPDATA[0]_tri_out);


--A1L25 is SRAMDATA[7]~0
--operation mode is bidir

A1L25 = SRAMDATA[7];

--SRAMDATA[7] is SRAMDATA[7]
--operation mode is bidir

SRAMDATA[7]_tri_out = TRI(C1L6, C1L711);
SRAMDATA[7] = BIDIR(SRAMDATA[7]_tri_out);


--A1L05 is SRAMDATA[6]~1
--operation mode is bidir

A1L05 = SRAMDATA[6];

--SRAMDATA[6] is SRAMDATA[6]
--operation mode is bidir

SRAMDATA[6]_tri_out = TRI(C1L7, C1L711);
SRAMDATA[6] = BIDIR(SRAMDATA[6]_tri_out);


--A1L84 is SRAMDATA[5]~2
--operation mode is bidir

A1L84 = SRAMDATA[5];

--SRAMDATA[5] is SRAMDATA[5]
--operation mode is bidir

SRAMDATA[5]_tri_out = TRI(C1L8, C1L711);
SRAMDATA[5] = BIDIR(SRAMDATA[5]_tri_out);


--A1L64 is SRAMDATA[4]~3
--operation mode is bidir

A1L64 = SRAMDATA[4];

--SRAMDATA[4] is SRAMDATA[4]
--operation mode is bidir

SRAMDATA[4]_tri_out = TRI(C1L9, C1L711);
SRAMDATA[4] = BIDIR(SRAMDATA[4]_tri_out);


--A1L44 is SRAMDATA[3]~4
--operation mode is bidir

A1L44 = SRAMDATA[3];

--SRAMDATA[3] is SRAMDATA[3]
--operation mode is bidir

SRAMDATA[3]_tri_out = TRI(C1L01, C1L711);
SRAMDATA[3] = BIDIR(SRAMDATA[3]_tri_out);


--A1L24 is SRAMDATA[2]~5
--operation mode is bidir

A1L24 = SRAMDATA[2];

--SRAMDATA[2] is SRAMDATA[2]
--operation mode is bidir

SRAMDATA[2]_tri_out = TRI(C1L11, C1L711);
SRAMDATA[2] = BIDIR(SRAMDATA[2]_tri_out);


--A1L04 is SRAMDATA[1]~6
--operation mode is bidir

A1L04 = SRAMDATA[1];

--SRAMDATA[1] is SRAMDATA[1]
--operation mode is bidir

SRAMDATA[1]_tri_out = TRI(C1L21, C1L711);
SRAMDATA[1] = BIDIR(SRAMDATA[1]_tri_out);


--A1L83 is SRAMDATA[0]~7
--operation mode is bidir

A1L83 = SRAMDATA[0];

--SRAMDATA[0] is SRAMDATA[0]
--operation mode is bidir

SRAMDATA[0]_tri_out = TRI(C1L31, C1L711);
SRAMDATA[0] = BIDIR(SRAMDATA[0]_tri_out);