epptop.map.eqn

在altera fpga中实现epp模式的并口通信程序

--C1_mem[1][6] is ram_dp_ar_aw:m1|mem[1][6]
C1_mem[1][6] = DFFEAS(C1L131, CLK,  ,  , C1L241,  ,  ,  ,  );


--C1L201 is ram_dp_ar_aw:m1|data_1_out[6]~123
C1L201 = C1L86 & C1L37 # !C1L86 & C1L37 & C1_mem[5][6] # !C1L37 & C1_mem[1][6];


--C1_mem[3][6] is ram_dp_ar_aw:m1|mem[3][6]
C1_mem[3][6] = DFFEAS(C1L131, CLK,  ,  , C1L661,  ,  ,  ,  );


--C1L301 is ram_dp_ar_aw:m1|data_1_out[6]~124
C1L301 = C1L86 & C1L201 & C1_mem[3][6] # !C1L201 & C1L101 # !C1L86 & C1L201;


--C1L011 is ram_dp_ar_aw:m1|data_1_out~110
C1L011 = SRAMWE & C1L301 & !SRAMCS & !SRAMOE;


--C1_mem[5][5] is ram_dp_ar_aw:m1|mem[5][5]
C1_mem[5][5] = DFFEAS(C1L231, CLK,  ,  , C1L981,  ,  ,  ,  );


--C1_mem[2][5] is ram_dp_ar_aw:m1|mem[2][5]
C1_mem[2][5] = DFFEAS(C1L231, CLK,  ,  , C1L751,  ,  ,  ,  );


--C1_mem[4][5] is ram_dp_ar_aw:m1|mem[4][5]
C1_mem[4][5] = DFFEAS(C1L231, CLK,  ,  , C1L871,  ,  ,  ,  );


--C1_mem[0][5] is ram_dp_ar_aw:m1|mem[0][5]
C1_mem[0][5] = DFFEAS(C1L231, CLK,  ,  , C1L721,  ,  ,  ,  );


--C1L59 is ram_dp_ar_aw:m1|data_1_out[5]~125
C1L59 = SRAMADDR[1] & SRAMADDR[2] # !SRAMADDR[1] & SRAMADDR[2] & C1_mem[4][5] # !SRAMADDR[2] & C1_mem[0][5];


--C1_mem[6][5] is ram_dp_ar_aw:m1|mem[6][5]
C1_mem[6][5] = DFFEAS(C1L231, CLK,  ,  , C1L602,  ,  ,  ,  );


--C1L69 is ram_dp_ar_aw:m1|data_1_out[5]~126
C1L69 = SRAMADDR[1] & C1L59 & C1_mem[6][5] # !C1L59 & C1_mem[2][5] # !SRAMADDR[1] & C1L59;


--C1_mem[1][5] is ram_dp_ar_aw:m1|mem[1][5]
C1_mem[1][5] = DFFEAS(C1L231, CLK,  ,  , C1L241,  ,  ,  ,  );


--C1L79 is ram_dp_ar_aw:m1|data_1_out[5]~127
C1L79 = C1L37 & C1L86 # !C1L37 & C1L86 & C1L69 # !C1L86 & C1_mem[1][5];


--C1_mem[3][5] is ram_dp_ar_aw:m1|mem[3][5]
C1_mem[3][5] = DFFEAS(C1L231, CLK,  ,  , C1L661,  ,  ,  ,  );


--C1L89 is ram_dp_ar_aw:m1|data_1_out[5]~128
C1L89 = C1L37 & C1L79 & C1_mem[3][5] # !C1L79 & C1_mem[5][5] # !C1L37 & C1L79;


--C1L111 is ram_dp_ar_aw:m1|data_1_out~111
C1L111 = SRAMWE & C1L89 & !SRAMCS & !SRAMOE;


--C1_mem[4][4] is ram_dp_ar_aw:m1|mem[4][4]
C1_mem[4][4] = DFFEAS(C1L331, CLK,  ,  , C1L871,  ,  ,  ,  );


--C1_mem[2][4] is ram_dp_ar_aw:m1|mem[2][4]
C1_mem[2][4] = DFFEAS(C1L331, CLK,  ,  , C1L751,  ,  ,  ,  );


--C1_mem[0][4] is ram_dp_ar_aw:m1|mem[0][4]
C1_mem[0][4] = DFFEAS(C1L331, CLK,  ,  , C1L721,  ,  ,  ,  );


--C1L09 is ram_dp_ar_aw:m1|data_1_out[4]~129
C1L09 = SRAMADDR[2] & SRAMADDR[1] # !SRAMADDR[2] & SRAMADDR[1] & C1_mem[2][4] # !SRAMADDR[1] & C1_mem[0][4];


--C1_mem[6][4] is ram_dp_ar_aw:m1|mem[6][4]
C1_mem[6][4] = DFFEAS(C1L331, CLK,  ,  , C1L602,  ,  ,  ,  );


--C1L19 is ram_dp_ar_aw:m1|data_1_out[4]~130
C1L19 = SRAMADDR[2] & C1L09 & C1_mem[6][4] # !C1L09 & C1_mem[4][4] # !SRAMADDR[2] & C1L09;


--C1_mem[5][4] is ram_dp_ar_aw:m1|mem[5][4]
C1_mem[5][4] = DFFEAS(C1L331, CLK,  ,  , C1L981,  ,  ,  ,  );


--C1_mem[1][4] is ram_dp_ar_aw:m1|mem[1][4]
C1_mem[1][4] = DFFEAS(C1L331, CLK,  ,  , C1L241,  ,  ,  ,  );


--C1L29 is ram_dp_ar_aw:m1|data_1_out[4]~131
C1L29 = C1L86 & C1L37 # !C1L86 & C1L37 & C1_mem[5][4] # !C1L37 & C1_mem[1][4];


--C1_mem[3][4] is ram_dp_ar_aw:m1|mem[3][4]
C1_mem[3][4] = DFFEAS(C1L331, CLK,  ,  , C1L661,  ,  ,  ,  );


--C1L39 is ram_dp_ar_aw:m1|data_1_out[4]~132
C1L39 = C1L86 & C1L29 & C1_mem[3][4] # !C1L29 & C1L19 # !C1L86 & C1L29;


--C1L211 is ram_dp_ar_aw:m1|data_1_out~112
C1L211 = SRAMWE & C1L39 & !SRAMCS & !SRAMOE;


--C1_mem[5][3] is ram_dp_ar_aw:m1|mem[5][3]
C1_mem[5][3] = DFFEAS(C1L431, CLK,  ,  , C1L981,  ,  ,  ,  );


--C1_mem[2][3] is ram_dp_ar_aw:m1|mem[2][3]
C1_mem[2][3] = DFFEAS(C1L431, CLK,  ,  , C1L751,  ,  ,  ,  );


--C1_mem[4][3] is ram_dp_ar_aw:m1|mem[4][3]
C1_mem[4][3] = DFFEAS(C1L431, CLK,  ,  , C1L871,  ,  ,  ,  );


--C1_mem[0][3] is ram_dp_ar_aw:m1|mem[0][3]
C1_mem[0][3] = DFFEAS(C1L431, CLK,  ,  , C1L721,  ,  ,  ,  );


--C1L58 is ram_dp_ar_aw:m1|data_1_out[3]~133
C1L58 = SRAMADDR[1] & SRAMADDR[2] # !SRAMADDR[1] & SRAMADDR[2] & C1_mem[4][3] # !SRAMADDR[2] & C1_mem[0][3];


--C1_mem[6][3] is ram_dp_ar_aw:m1|mem[6][3]
C1_mem[6][3] = DFFEAS(C1L431, CLK,  ,  , C1L602,  ,  ,  ,  );


--C1L68 is ram_dp_ar_aw:m1|data_1_out[3]~134
C1L68 = SRAMADDR[1] & C1L58 & C1_mem[6][3] # !C1L58 & C1_mem[2][3] # !SRAMADDR[1] & C1L58;


--C1_mem[1][3] is ram_dp_ar_aw:m1|mem[1][3]
C1_mem[1][3] = DFFEAS(C1L431, CLK,  ,  , C1L241,  ,  ,  ,  );


--C1L78 is ram_dp_ar_aw:m1|data_1_out[3]~135
C1L78 = C1L37 & C1L86 # !C1L37 & C1L86 & C1L68 # !C1L86 & C1_mem[1][3];


--C1_mem[3][3] is ram_dp_ar_aw:m1|mem[3][3]
C1_mem[3][3] = DFFEAS(C1L431, CLK,  ,  , C1L661,  ,  ,  ,  );


--C1L88 is ram_dp_ar_aw:m1|data_1_out[3]~136
C1L88 = C1L37 & C1L78 & C1_mem[3][3] # !C1L78 & C1_mem[5][3] # !C1L37 & C1L78;


--C1L311 is ram_dp_ar_aw:m1|data_1_out~113
C1L311 = SRAMWE & C1L88 & !SRAMCS & !SRAMOE;


--C1_mem[4][2] is ram_dp_ar_aw:m1|mem[4][2]
C1_mem[4][2] = DFFEAS(C1L531, CLK,  ,  , C1L871,  ,  ,  ,  );


--C1_mem[2][2] is ram_dp_ar_aw:m1|mem[2][2]
C1_mem[2][2] = DFFEAS(C1L531, CLK,  ,  , C1L751,  ,  ,  ,  );


--C1_mem[0][2] is ram_dp_ar_aw:m1|mem[0][2]
C1_mem[0][2] = DFFEAS(C1L531, CLK,  ,  , C1L721,  ,  ,  ,  );


--C1L08 is ram_dp_ar_aw:m1|data_1_out[2]~137
C1L08 = SRAMADDR[2] & SRAMADDR[1] # !SRAMADDR[2] & SRAMADDR[1] & C1_mem[2][2] # !SRAMADDR[1] & C1_mem[0][2];


--C1_mem[6][2] is ram_dp_ar_aw:m1|mem[6][2]
C1_mem[6][2] = DFFEAS(C1L531, CLK,  ,  , C1L602,  ,  ,  ,  );


--C1L18 is ram_dp_ar_aw:m1|data_1_out[2]~138
C1L18 = SRAMADDR[2] & C1L08 & C1_mem[6][2] # !C1L08 & C1_mem[4][2] # !SRAMADDR[2] & C1L08;


--C1_mem[5][2] is ram_dp_ar_aw:m1|mem[5][2]
C1_mem[5][2] = DFFEAS(C1L531, CLK,  ,  , C1L981,  ,  ,  ,  );


--C1_mem[1][2] is ram_dp_ar_aw:m1|mem[1][2]
C1_mem[1][2] = DFFEAS(C1L531, CLK,  ,  , C1L241,  ,  ,  ,  );


--C1L28 is ram_dp_ar_aw:m1|data_1_out[2]~139
C1L28 = C1L86 & C1L37 # !C1L86 & C1L37 & C1_mem[5][2] # !C1L37 & C1_mem[1][2];


--C1_mem[3][2] is ram_dp_ar_aw:m1|mem[3][2]
C1_mem[3][2] = DFFEAS(C1L531, CLK,  ,  , C1L661,  ,  ,  ,  );


--C1L38 is ram_dp_ar_aw:m1|data_1_out[2]~140
C1L38 = C1L86 & C1L28 & C1_mem[3][2] # !C1L28 & C1L18 # !C1L86 & C1L28;


--C1L411 is ram_dp_ar_aw:m1|data_1_out~114
C1L411 = SRAMWE & C1L38 & !SRAMCS & !SRAMOE;


--C1_mem[5][1] is ram_dp_ar_aw:m1|mem[5][1]
C1_mem[5][1] = DFFEAS(C1L631, CLK,  ,  , C1L981,  ,  ,  ,  );


--C1_mem[2][1] is ram_dp_ar_aw:m1|mem[2][1]
C1_mem[2][1] = DFFEAS(C1L631, CLK,  ,  , C1L751,  ,  ,  ,  );


--C1_mem[4][1] is ram_dp_ar_aw:m1|mem[4][1]
C1_mem[4][1] = DFFEAS(C1L631, CLK,  ,  , C1L871,  ,  ,  ,  );


--C1_mem[0][1] is ram_dp_ar_aw:m1|mem[0][1]
C1_mem[0][1] = DFFEAS(C1L631, CLK,  ,  , C1L721,  ,  ,  ,  );


--C1L57 is ram_dp_ar_aw:m1|data_1_out[1]~141
C1L57 = SRAMADDR[1] & SRAMADDR[2] # !SRAMADDR[1] & SRAMADDR[2] & C1_mem[4][1] # !SRAMADDR[2] & C1_mem[0][1];


--C1_mem[6][1] is ram_dp_ar_aw:m1|mem[6][1]
C1_mem[6][1] = DFFEAS(C1L631, CLK,  ,  , C1L602,  ,  ,  ,  );


--C1L67 is ram_dp_ar_aw:m1|data_1_out[1]~142
C1L67 = SRAMADDR[1] & C1L57 & C1_mem[6][1] # !C1L57 & C1_mem[2][1] # !SRAMADDR[1] & C1L57;


--C1_mem[1][1] is ram_dp_ar_aw:m1|mem[1][1]
C1_mem[1][1] = DFFEAS(C1L631, CLK,  ,  , C1L241,  ,  ,  ,  );


--C1L77 is ram_dp_ar_aw:m1|data_1_out[1]~143
C1L77 = C1L37 & C1L86 # !C1L37 & C1L86 & C1L67 # !C1L86 & C1_mem[1][1];


--C1_mem[3][1] is ram_dp_ar_aw:m1|mem[3][1]
C1_mem[3][1] = DFFEAS(C1L631, CLK,  ,  , C1L661,  ,  ,  ,  );


--C1L87 is ram_dp_ar_aw:m1|data_1_out[1]~144
C1L87 = C1L37 & C1L77 & C1_mem[3][1] # !C1L77 & C1_mem[5][1] # !C1L37 & C1L77;


--C1L511 is ram_dp_ar_aw:m1|data_1_out~115
C1L511 = SRAMWE & C1L87 & !SRAMCS & !SRAMOE;


--C1_mem[4][0] is ram_dp_ar_aw:m1|mem[4][0]
C1_mem[4][0] = DFFEAS(C1L731, CLK,  ,  , C1L871,  ,  ,  ,  );


--C1_mem[2][0] is ram_dp_ar_aw:m1|mem[2][0]
C1_mem[2][0] = DFFEAS(C1L731, CLK,  ,  , C1L751,  ,  ,  ,  );


--C1_mem[0][0] is ram_dp_ar_aw:m1|mem[0][0]
C1_mem[0][0] = DFFEAS(C1L731, CLK,  ,  , C1L721,  ,  ,  ,  );


--C1L96 is ram_dp_ar_aw:m1|data_1_out[0]~145
C1L96 = SRAMADDR[2] & SRAMADDR[1] # !SRAMADDR[2] & SRAMADDR[1] & C1_mem[2][0] # !SRAMADDR[1] & C1_mem[0][0];


--C1_mem[6][0] is ram_dp_ar_aw:m1|mem[6][0]
C1_mem[6][0] = DFFEAS(C1L731, CLK,  ,  , C1L602,  ,  ,  ,  );


--C1L07 is ram_dp_ar_aw:m1|data_1_out[0]~146
C1L07 = SRAMADDR[2] & C1L96 & C1_mem[6][0] # !C1L96 & C1_mem[4][0] # !SRAMADDR[2] & C1L96;


--C1_mem[5][0] is ram_dp_ar_aw:m1|mem[5][0]
C1_mem[5][0] = DFFEAS(C1L731, CLK,  ,  , C1L981,  ,  ,  ,  );


--C1_mem[1][0] is ram_dp_ar_aw:m1|mem[1][0]
C1_mem[1][0] = DFFEAS(C1L731, CLK,  ,  , C1L241,  ,  ,  ,  );


--C1L17 is ram_dp_ar_aw:m1|data_1_out[0]~147
C1L17 = C1L86 & C1L37 # !C1L86 & C1L37 & C1_mem[5][0] # !C1L37 & C1_mem[1][0];


--C1_mem[3][0] is ram_dp_ar_aw:m1|mem[3][0]
C1_mem[3][0] = DFFEAS(C1L731, CLK,  ,  , C1L661,  ,  ,  ,  );


--C1L27 is ram_dp_ar_aw:m1|data_1_out[0]~148
C1L27 = C1L86 & C1L17 & C1_mem[3][0] # !C1L17 & C1L07 # !C1L86 & C1L17;


--C1L611 is ram_dp_ar_aw:m1|data_1_out~116
C1L611 = SRAMWE & C1L27 & !SRAMCS & !SRAMOE;


--B1L83 is EPP2SRAM:M0|epp_datain~66
B1L83 = A1L82 & RST;


--B1L62 is EPP2SRAM:M0|cmd~117
B1L62 = !B1_epp_state.EPP_IDLE & !B1_EPP_Write;


--C1L55 is ram_dp_ar_aw:m1|data_0_out[7]~323
C1L55 = B1L9 & B1L11 # B1L01;


--C1L15 is ram_dp_ar_aw:m1|data_0_out[7]~117
C1L15 = B1L01 & B1L11 # !B1L01 & B1L11 & C1_mem[4][7] # !B1L11 & C1_mem[0][7];


--C1L25 is ram_dp_ar_aw:m1|data_0_out[7]~118
C1L25 = B1L01 & C1L15 & C1_mem[6][7] # !C1L15 & C1_mem[2][7] # !B1L01 & C1L15;


--C1L65 is ram_dp_ar_aw:m1|data_0_out[7]~324
C1L65 = B1L9 & B1_cmd[0] & !B1_sram_waddr[1] # !B1_cmd[0] & !B1_sram_raddr[1];


--C1L35 is ram_dp_ar_aw:m1|data_0_out[7]~119
C1L35 = C1L55 & !C1L65 # !C1L55 & C1L65 & C1_mem[1][7] # !C1L65 & C1L25;


--C1L45 is ram_dp_ar_aw:m1|data_0_out[7]~120
C1L45 = C1L55 & C1L35 & C1_mem[3][7] # !C1L35 & C1_mem[5][7] # !C1L55 & C1L35;


--B1_SRAM_CE is EPP2SRAM:M0|SRAM_CE
B1_SRAM_CE = DFFEAS(B1L31, CLK,  ,  ,  ,  ,  ,  ,  );


--C1L85 is ram_dp_ar_aw:m1|data_0_out~109
C1L85 = C1L45 & !B1_cmd[0] & !B1_SRAM_CE;


--B1L72 is EPP2SRAM:M0|cmd~118
B1L72 = B1L62 & B1_EPP_AddressStrobe & B1_cmd[0] # !B1_EPP_AddressStrobe & A1L41 # !B1L62 & B1_cmd[0];


--B1L93 is EPP2SRAM:M0|epp_datain~69
B1L93 = A1L62 & RST;


--C1L64 is ram_dp_ar_aw:m1|data_0_out[6]~121
C1L64 = B1L11 & B1L01 # !B1L11 & B1L01 & C1_mem[2][6] # !B1L01 & C1_mem[0][6];


--C1L74 is ram_dp_ar_aw:m1|data_0_out[6]~122
C1L74 = B1L11 & C1L64 & C1_mem[6][6] # !C1L64 & C1_mem[4][6] # !B1L11 & C1L64;


--C1L84 is ram_dp_ar_aw:m1|data_0_out[6]~123
C1L84 = C1L65 & C1L55 & C1_mem[5][6] # !C1L55 & C1_mem[1][6] # !C1L65 & C1L55;


--C1L94 is ram_dp_ar_aw:m1|data_0_out[6]~124
C1L94 = C1L65 & C1L84 # !C1L65 & C1L84 & C1_mem[3][6] # !C1L84 & C1L74;


--C1L95 is ram_dp_ar_aw:m1|data_0_out~110
C1L95 = C1L94 & !B1_cmd[0] & !B1_SRAM_CE;


--B1L04 is EPP2SRAM:M0|epp_datain~70
B1L04 = A1L42 & RST;


--C1L14 is ram_dp_ar_aw:m1|data_0_out[5]~125
C1L14 = B1L01 & B1L11 # !B1L01 & B1L11 & C1_mem[4][5] # !B1L11 & C1_mem[0][5];


--C1L24 is ram_dp_ar_aw:m1|data_0_out[5]~126
C1L24 = B1L01 & C1L14 & C1_mem[6][5] # !C1L14 & C1_mem[2][5] # !B1L01 & C1L14;


--C1L34 is ram_dp_ar_aw:m1|data_0_out[5]~127
C1L34 = C1L55 & !C1L65 # !C1L55 & C1L65 & C1_mem[1][5] # !C1L65 & C1L24;


--C1L44 is ram_dp_ar_aw:m1|data_0_out[5]~128
C1L44 = C1L55 & C1L34 & C1_mem[3][5] # !C1L34 & C1_mem[5][5] # !C1L55 & C1L34;


--C1L06 is ram_dp_ar_aw:m1|data_0_out~111
C1L06 = C1L44 & !B1_cmd[0] & !B1_SRAM_CE;


--B1L14 is EPP2SRAM:M0|epp_datain~71
B1L14 = A1L22 & RST;


--C1L63 is ram_dp_ar_aw:m1|data_0_out[4]~129
C1L63 = B1L11 & B1L01 # !B1L11 & B1L01 & C1_mem[2][4] # !B1L01 & C1_mem[0][4];


--C1L73 is ram_dp_ar_aw:m1|data_0_out[4]~130
C1L73 = B1L11 & C1L63 & C1_mem[6][4] # !C1L63 & C1_mem[4][4] # !B1L11 & C1L63;


--C1L83 is ram_dp_ar_aw:m1|data_0_out[4]~131
C1L83 = C1L65 & C1L55 & C1_mem[5][4] # !C1L55 & C1_mem[1][4] # !C1L65 & C1L55;


--C1L93 is ram_dp_ar_aw:m1|data_0_out[4]~132
C1L93 = C1L65 & C1L83 # !C1L65 & C1L83 & C1_mem[3][4] # !C1L83 & C1L73;


--C1L16 is ram_dp_ar_aw:m1|data_0_out~112
C1L16 = C1L93 & !B1_cmd[0] & !B1_SRAM_CE;


--B1L24 is EPP2SRAM:M0|epp_datain~72
B1L24 = A1L02 & RST;


--C1L13 is ram_dp_ar_aw:m1|data_0_out[3]~133
C1L13 = B1L01 & B1L11 # !B1L01 & B1L11 & C1_mem[4][3] # !B1L11 & C1_mem[0][3];


--C1L23 is ram_dp_ar_aw:m1|data_0_out[3]~134
C1L23 = B1L01 & C1L13 & C1_mem[6][3] # !C1L13 & C1_mem[2][3] # !B1L01 & C1L13;


--C1L33 is ram_dp_ar_aw:m1|data_0_out[3]~135
C1L33 = C1L55 & !C1L65 # !C1L55 & C1L65 & C1_mem[1][3] # !C1L65 & C1L23;


--C1L43 is ram_dp_ar_aw:m1|data_0_out[3]~136
C1L43 = C1L55 & C1L33 & C1_mem[3][3] # !C1L33 & C1_mem[5][3] # !C1L55 & C1L33;


--C1L26 is ram_dp_ar_aw:m1|data_0_out~113
C1L26 = C1L43 & !B1_cmd[0] & !B1_SRAM_CE;


--B1L34 is EPP2SRAM:M0|epp_datain~73
B1L34 = A1L81 & RST;


--C1L62 is ram_dp_ar_aw:m1|data_0_out[2]~137
C1L62 = B1L11 & B1L01 # !B1L11 & B1L01 & C1_mem[2][2] # !B1L01 & C1_mem[0][2];


--C1L72 is ram_dp_ar_aw:m1|data_0_out[2]~138
C1L72 = B1L11 & C1L62 & C1_mem[6][2] # !C1L62 & C1_mem[4][2] # !B1L11 & C1L62;


--C1L82 is ram_dp_ar_aw:m1|data_0_out[2]~139
C1L82 = C1L65 & C1L55 & C1_mem[5][2] # !C1L55 & C1_mem[1][2] # !C1L65 & C1L55;


--C1L92 is ram_dp_ar_aw:m1|data_0_out[2]~140
C1L92 = C1L65 & C1L82 # !C1L65 & C1L82 & C1_mem[3][2] # !C1L82 & C1L72;


--C1L36 is ram_dp_ar_aw:m1|data_0_out~114
C1L36 = C1L92 & !B1_cmd[0] & !B1_SRAM_CE;


--B1L32 is EPP2SRAM:M0|add~87
B1L32 = B1_sram_waddr[2] $ (B1_EPP_DataStrobe & B1_sram_waddr[1] & B1_sram_waddr[0]);


--B1L78 is EPP2SRAM:M0|sram_waddr[0]~19
B1L78 = B1_epp_state.EPP_WAIT_DATAWRITE # !RST;