epptop.map.eqn

在altera fpga中实现epp模式的并口通信程序

--B1_EPP_Wait is EPP2SRAM:M0|EPP_Wait
B1_EPP_Wait = DFFEAS(B1L71, CLK,  ,  ,  ,  ,  , !RST,  );


--B1_EPP_DataStrobe is EPP2SRAM:M0|EPP_DataStrobe
B1_EPP_DataStrobe = DFFEAS(B1L4, CLK,  ,  ,  ,  ,  ,  ,  );


--B1_EPP_AddressStrobe is EPP2SRAM:M0|EPP_AddressStrobe
B1_EPP_AddressStrobe = DFFEAS(B1L2, CLK,  ,  ,  ,  ,  ,  ,  );


--B1_epp_state.EPP_WAIT_ADDRWRITE is EPP2SRAM:M0|epp_state.EPP_WAIT_ADDRWRITE
B1_epp_state.EPP_WAIT_ADDRWRITE = DFFEAS(B1L27, CLK,  ,  ,  ,  ,  ,  ,  );


--B1_epp_state.EPP_WAIT_ADDRREAD is EPP2SRAM:M0|epp_state.EPP_WAIT_ADDRREAD
B1_epp_state.EPP_WAIT_ADDRREAD = DFFEAS(B1L37, CLK,  ,  ,  ,  ,  ,  ,  );


--B1L41 is EPP2SRAM:M0|Select~208
B1L41 = !B1_epp_state.EPP_WAIT_ADDRWRITE & !B1_epp_state.EPP_WAIT_ADDRREAD;


--B1_epp_state.EPP_WAIT_DATAWRITE is EPP2SRAM:M0|epp_state.EPP_WAIT_DATAWRITE
B1_epp_state.EPP_WAIT_DATAWRITE = DFFEAS(B1L67, CLK,  ,  ,  ,  ,  ,  ,  );


--B1_epp_state.EPP_WAIT_DATAREAD is EPP2SRAM:M0|epp_state.EPP_WAIT_DATAREAD
B1_epp_state.EPP_WAIT_DATAREAD = DFFEAS(B1L77, CLK,  ,  ,  ,  ,  ,  ,  );


--B1L51 is EPP2SRAM:M0|Select~209
B1L51 = !B1_epp_state.EPP_WAIT_DATAWRITE & !B1_epp_state.EPP_WAIT_DATAREAD;


--B1L61 is EPP2SRAM:M0|Select~210
B1L61 = B1_EPP_DataStrobe & !B1_EPP_AddressStrobe & !B1L41 # !B1_EPP_DataStrobe & !B1_EPP_AddressStrobe & !B1L41 # !B1L51;


--B1_epp_state.EPP_IDLE is EPP2SRAM:M0|epp_state.EPP_IDLE
B1_epp_state.EPP_IDLE = DFFEAS(B1L97, CLK,  ,  ,  ,  ,  ,  ,  );


--B1L96 is EPP2SRAM:M0|epp_state~666
B1L96 = B1_EPP_DataStrobe & B1_EPP_AddressStrobe;


--B1L71 is EPP2SRAM:M0|Select~211
B1L71 = B1_EPP_Wait & B1L61 # !B1_epp_state.EPP_IDLE & !B1L96 # !B1_EPP_Wait & !B1_epp_state.EPP_IDLE & !B1L96;


--B1L4 is EPP2SRAM:M0|EPP_DataStrobe~3
B1L4 = DS # !RST;


--B1L2 is EPP2SRAM:M0|EPP_AddressStrobe~3
B1L2 = AS # !RST;


--B1L07 is EPP2SRAM:M0|epp_state~667
B1L07 = B1L41 & B1L51 # !B1_EPP_DataStrobe # !B1L41 & !B1_EPP_AddressStrobe & B1L51 # !B1_EPP_DataStrobe;


--B1L17 is EPP2SRAM:M0|epp_state~668
B1L17 = RST & B1_epp_state.EPP_IDLE & B1L07 # !B1_epp_state.EPP_IDLE & !B1_EPP_AddressStrobe;


--B1_EPP_Write is EPP2SRAM:M0|EPP_Write
B1_EPP_Write = DFFEAS(B1L8, CLK,  ,  ,  ,  ,  ,  ,  );


--B1L27 is EPP2SRAM:M0|epp_state~669
B1L27 = B1L17 & B1_epp_state.EPP_IDLE & B1_epp_state.EPP_WAIT_ADDRWRITE # !B1_epp_state.EPP_IDLE & !B1_EPP_Write;


--B1L37 is EPP2SRAM:M0|epp_state~670
B1L37 = B1L17 & B1_epp_state.EPP_IDLE & B1_epp_state.EPP_WAIT_ADDRREAD # !B1_epp_state.EPP_IDLE & B1_EPP_Write;


--B1L47 is EPP2SRAM:M0|epp_state~671
B1L47 = B1_EPP_AddressStrobe & !B1_EPP_DataStrobe;


--B1L57 is EPP2SRAM:M0|epp_state~672
B1L57 = RST & B1_epp_state.EPP_IDLE & B1L07 # !B1_epp_state.EPP_IDLE & B1L47;


--B1L67 is EPP2SRAM:M0|epp_state~673
B1L67 = B1L57 & B1_epp_state.EPP_IDLE & B1_epp_state.EPP_WAIT_DATAWRITE # !B1_epp_state.EPP_IDLE & !B1_EPP_Write;


--B1L77 is EPP2SRAM:M0|epp_state~674
B1L77 = B1L57 & B1_epp_state.EPP_IDLE & B1_epp_state.EPP_WAIT_DATAREAD # !B1_epp_state.EPP_IDLE & B1_EPP_Write;


--B1L5 is EPP2SRAM:M0|EPP_Data~26
B1L5 = B1_epp_state.EPP_WAIT_DATAREAD # B1_epp_state.EPP_WAIT_ADDRREAD;


--B1L87 is EPP2SRAM:M0|epp_state~675
B1L87 = B1_epp_state.EPP_WAIT_DATAWRITE # B1_epp_state.EPP_WAIT_ADDRWRITE # B1L96 # B1L5;


--B1L97 is EPP2SRAM:M0|epp_state~676
B1L97 = RST & B1L07 & B1_epp_state.EPP_IDLE # !B1L87;


--B1_epp_dataout[7] is EPP2SRAM:M0|epp_dataout[7]
B1_epp_dataout[7] = DFFEAS(B1L95, CLK,  ,  , B1L85,  ,  ,  ,  );


--B1_epp_dataout[6] is EPP2SRAM:M0|epp_dataout[6]
B1_epp_dataout[6] = DFFEAS(B1L06, CLK,  ,  , B1L85,  ,  ,  ,  );


--B1_epp_dataout[5] is EPP2SRAM:M0|epp_dataout[5]
B1_epp_dataout[5] = DFFEAS(B1L16, CLK,  ,  , B1L85,  ,  ,  ,  );


--B1_epp_dataout[4] is EPP2SRAM:M0|epp_dataout[4]
B1_epp_dataout[4] = DFFEAS(B1L26, CLK,  ,  , B1L85,  ,  ,  ,  );


--B1_epp_dataout[3] is EPP2SRAM:M0|epp_dataout[3]
B1_epp_dataout[3] = DFFEAS(B1L36, CLK,  ,  , B1L85,  ,  ,  ,  );


--B1_epp_dataout[2] is EPP2SRAM:M0|epp_dataout[2]
B1_epp_dataout[2] = DFFEAS(B1L25, CLK,  ,  , B1L85,  ,  , !RST,  );


--B1_epp_dataout[1] is EPP2SRAM:M0|epp_dataout[1]
B1_epp_dataout[1] = DFFEAS(B1L05, CLK,  ,  , B1L85,  ,  , !RST,  );


--B1_epp_dataout[0] is EPP2SRAM:M0|epp_dataout[0]
B1_epp_dataout[0] = DFFEAS(B1L84, CLK,  ,  , B1L85,  ,  , !RST,  );


--C1_data_1_out[7] is ram_dp_ar_aw:m1|data_1_out[7]
C1_data_1_out[7] = DFFEAS(C1L901, CLK,  ,  ,  ,  ,  ,  ,  );


--C1L3Q is ram_dp_ar_aw:m1|always1~2
C1L3Q = DFFEAS(C1L4, CLK,  ,  ,  ,  ,  ,  ,  );


--C1L6 is ram_dp_ar_aw:m1|always2~34
C1L6 = C1_data_1_out[7] # !C1L3Q;


--C1L711 is ram_dp_ar_aw:m1|data_1~46
C1L711 = SRAMWE & !SRAMCS & !SRAMOE;


--C1_data_1_out[6] is ram_dp_ar_aw:m1|data_1_out[6]
C1_data_1_out[6] = DFFEAS(C1L011, CLK,  ,  ,  ,  ,  ,  ,  );


--C1L7 is ram_dp_ar_aw:m1|always2~35
C1L7 = C1_data_1_out[6] # !C1L3Q;


--C1_data_1_out[5] is ram_dp_ar_aw:m1|data_1_out[5]
C1_data_1_out[5] = DFFEAS(C1L111, CLK,  ,  ,  ,  ,  ,  ,  );


--C1L8 is ram_dp_ar_aw:m1|always2~36
C1L8 = C1_data_1_out[5] # !C1L3Q;


--C1_data_1_out[4] is ram_dp_ar_aw:m1|data_1_out[4]
C1_data_1_out[4] = DFFEAS(C1L211, CLK,  ,  ,  ,  ,  ,  ,  );


--C1L9 is ram_dp_ar_aw:m1|always2~37
C1L9 = C1_data_1_out[4] # !C1L3Q;


--C1_data_1_out[3] is ram_dp_ar_aw:m1|data_1_out[3]
C1_data_1_out[3] = DFFEAS(C1L311, CLK,  ,  ,  ,  ,  ,  ,  );


--C1L01 is ram_dp_ar_aw:m1|always2~38
C1L01 = C1_data_1_out[3] # !C1L3Q;


--C1_data_1_out[2] is ram_dp_ar_aw:m1|data_1_out[2]
C1_data_1_out[2] = DFFEAS(C1L411, CLK,  ,  ,  ,  ,  ,  ,  );


--C1L11 is ram_dp_ar_aw:m1|always2~39
C1L11 = C1_data_1_out[2] # !C1L3Q;


--C1_data_1_out[1] is ram_dp_ar_aw:m1|data_1_out[1]
C1_data_1_out[1] = DFFEAS(C1L511, CLK,  ,  ,  ,  ,  ,  ,  );


--C1L21 is ram_dp_ar_aw:m1|always2~40
C1L21 = C1_data_1_out[1] # !C1L3Q;


--C1_data_1_out[0] is ram_dp_ar_aw:m1|data_1_out[0]
C1_data_1_out[0] = DFFEAS(C1L611, CLK,  ,  ,  ,  ,  ,  ,  );


--C1L31 is ram_dp_ar_aw:m1|always2~41
C1L31 = C1_data_1_out[0] # !C1L3Q;


--B1L8 is EPP2SRAM:M0|EPP_Write~3
B1L8 = WRITE # !RST;


--B1_epp_datain[7] is EPP2SRAM:M0|epp_datain[7]
B1_epp_datain[7] = DFFEAS(B1L83, CLK,  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[7] is ram_dp_ar_aw:m1|data_0_out[7]
C1_data_0_out[7] = DFFEAS(C1L85, CLK,  ,  ,  ,  ,  ,  ,  );


--B1_cmd[0] is EPP2SRAM:M0|cmd[0]
B1_cmd[0] = DFFEAS(B1L72, CLK,  ,  ,  ,  ,  , !RST,  );


--A1L8 is ADD_DATA[7]~432
A1L8 = B1_cmd[0] & B1_epp_datain[7] # !B1_cmd[0] & C1_data_0_out[7] # !C1L3Q;


--B1L95 is EPP2SRAM:M0|epp_dataout~519
B1L95 = B1_EPP_AddressStrobe & RST & A1L8;


--B1L85 is EPP2SRAM:M0|epp_dataout[7]~520
B1L85 = !B1_epp_state.EPP_IDLE & !B1L96 & B1_EPP_Write # !RST;


--B1_epp_datain[6] is EPP2SRAM:M0|epp_datain[6]
B1_epp_datain[6] = DFFEAS(B1L93, CLK,  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[6] is ram_dp_ar_aw:m1|data_0_out[6]
C1_data_0_out[6] = DFFEAS(C1L95, CLK,  ,  ,  ,  ,  ,  ,  );


--A1L7 is ADD_DATA[6]~433
A1L7 = B1_cmd[0] & B1_epp_datain[6] # !B1_cmd[0] & C1_data_0_out[6] # !C1L3Q;


--B1L06 is EPP2SRAM:M0|epp_dataout~521
B1L06 = B1_EPP_AddressStrobe & RST & A1L7;


--B1_epp_datain[5] is EPP2SRAM:M0|epp_datain[5]
B1_epp_datain[5] = DFFEAS(B1L04, CLK,  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[5] is ram_dp_ar_aw:m1|data_0_out[5]
C1_data_0_out[5] = DFFEAS(C1L06, CLK,  ,  ,  ,  ,  ,  ,  );


--A1L6 is ADD_DATA[5]~434
A1L6 = B1_cmd[0] & B1_epp_datain[5] # !B1_cmd[0] & C1_data_0_out[5] # !C1L3Q;


--B1L16 is EPP2SRAM:M0|epp_dataout~522
B1L16 = B1_EPP_AddressStrobe & RST & A1L6;


--B1_epp_datain[4] is EPP2SRAM:M0|epp_datain[4]
B1_epp_datain[4] = DFFEAS(B1L14, CLK,  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[4] is ram_dp_ar_aw:m1|data_0_out[4]
C1_data_0_out[4] = DFFEAS(C1L16, CLK,  ,  ,  ,  ,  ,  ,  );


--A1L5 is ADD_DATA[4]~435
A1L5 = B1_cmd[0] & B1_epp_datain[4] # !B1_cmd[0] & C1_data_0_out[4] # !C1L3Q;


--B1L26 is EPP2SRAM:M0|epp_dataout~523
B1L26 = B1_EPP_AddressStrobe & RST & A1L5;


--B1_epp_datain[3] is EPP2SRAM:M0|epp_datain[3]
B1_epp_datain[3] = DFFEAS(B1L24, CLK,  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[3] is ram_dp_ar_aw:m1|data_0_out[3]
C1_data_0_out[3] = DFFEAS(C1L26, CLK,  ,  ,  ,  ,  ,  ,  );


--A1L4 is ADD_DATA[3]~436
A1L4 = B1_cmd[0] & B1_epp_datain[3] # !B1_cmd[0] & C1_data_0_out[3] # !C1L3Q;


--B1L36 is EPP2SRAM:M0|epp_dataout~524
B1L36 = B1_EPP_AddressStrobe & RST & A1L4;


--B1_epp_datain[2] is EPP2SRAM:M0|epp_datain[2]
B1_epp_datain[2] = DFFEAS(B1L34, CLK,  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[2] is ram_dp_ar_aw:m1|data_0_out[2]
C1_data_0_out[2] = DFFEAS(C1L36, CLK,  ,  ,  ,  ,  ,  ,  );


--A1L3 is ADD_DATA[2]~437
A1L3 = B1_cmd[0] & B1_epp_datain[2] # !B1_cmd[0] & C1_data_0_out[2] # !C1L3Q;


--B1_sram_waddr[2] is EPP2SRAM:M0|sram_waddr[2]
B1_sram_waddr[2] = DFFEAS(B1L32, CLK,  ,  , B1L78,  ,  , !RST,  );


--B1_sram_raddr[2] is EPP2SRAM:M0|sram_raddr[2]
B1_sram_raddr[2] = DFFEAS(B1L02, CLK,  ,  , B1L28,  ,  , !RST,  );


--B1L11 is EPP2SRAM:M0|SRAM_ADDR[2]~125
B1L11 = B1_cmd[0] & B1_sram_waddr[2] # !B1_cmd[0] & B1_sram_raddr[2];


--B1L25 is EPP2SRAM:M0|epp_dataout[2]~525
B1L25 = B1_EPP_AddressStrobe & A1L3 # !B1_EPP_AddressStrobe & B1L11;


--B1_epp_datain[1] is EPP2SRAM:M0|epp_datain[1]
B1_epp_datain[1] = DFFEAS(B1L44, CLK,  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[1] is ram_dp_ar_aw:m1|data_0_out[1]
C1_data_0_out[1] = DFFEAS(C1L46, CLK,  ,  ,  ,  ,  ,  ,  );


--A1L2 is ADD_DATA[1]~438
A1L2 = B1_cmd[0] & B1_epp_datain[1] # !B1_cmd[0] & C1_data_0_out[1] # !C1L3Q;


--B1_sram_waddr[1] is EPP2SRAM:M0|sram_waddr[1]
B1_sram_waddr[1] = DFFEAS(B1L22, CLK,  ,  , B1L78,  ,  , !RST,  );


--B1_sram_raddr[1] is EPP2SRAM:M0|sram_raddr[1]
B1_sram_raddr[1] = DFFEAS(B1L91, CLK,  ,  , B1L28,  ,  , !RST,  );


--B1L01 is EPP2SRAM:M0|SRAM_ADDR[1]~126
B1L01 = B1_cmd[0] & B1_sram_waddr[1] # !B1_cmd[0] & B1_sram_raddr[1];


--B1L05 is EPP2SRAM:M0|epp_dataout[1]~526
B1L05 = B1_EPP_AddressStrobe & A1L2 # !B1_EPP_AddressStrobe & B1L01;


--B1_epp_datain[0] is EPP2SRAM:M0|epp_datain[0]
B1_epp_datain[0] = DFFEAS(B1L54, CLK,  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[0] is ram_dp_ar_aw:m1|data_0_out[0]
C1_data_0_out[0] = DFFEAS(C1L56, CLK,  ,  ,  ,  ,  ,  ,  );


--A1L1 is ADD_DATA[0]~439
A1L1 = B1_cmd[0] & B1_epp_datain[0] # !B1_cmd[0] & C1_data_0_out[0] # !C1L3Q;


--B1_sram_waddr[0] is EPP2SRAM:M0|sram_waddr[0]
B1_sram_waddr[0] = DFFEAS(B1L12, CLK,  ,  , B1L78,  ,  , !RST,  );


--B1_sram_raddr[0] is EPP2SRAM:M0|sram_raddr[0]
B1_sram_raddr[0] = DFFEAS(B1L81, CLK,  ,  , B1L28,  ,  , !RST,  );


--B1L9 is EPP2SRAM:M0|SRAM_ADDR[0]~127
B1L9 = B1_cmd[0] & B1_sram_waddr[0] # !B1_cmd[0] & B1_sram_raddr[0];


--B1L84 is EPP2SRAM:M0|epp_dataout[0]~527
B1L84 = B1_EPP_AddressStrobe & A1L1 # !B1_EPP_AddressStrobe & B1L9;


--C1_mem[5][7] is ram_dp_ar_aw:m1|mem[5][7]
C1_mem[5][7] = DFFEAS(C1L031, CLK,  ,  , C1L981,  ,  ,  ,  );


--C1L37 is ram_dp_ar_aw:m1|data_1_out[0]~293
C1L37 = SRAMADDR[0] & SRAMADDR[2] # SRAMADDR[1];


--C1_mem[2][7] is ram_dp_ar_aw:m1|mem[2][7]
C1_mem[2][7] = DFFEAS(C1L031, CLK,  ,  , C1L751,  ,  ,  ,  );


--C1_mem[4][7] is ram_dp_ar_aw:m1|mem[4][7]
C1_mem[4][7] = DFFEAS(C1L031, CLK,  ,  , C1L871,  ,  ,  ,  );


--C1_mem[0][7] is ram_dp_ar_aw:m1|mem[0][7]
C1_mem[0][7] = DFFEAS(C1L031, CLK,  ,  , C1L721,  ,  ,  ,  );


--C1L501 is ram_dp_ar_aw:m1|data_1_out[7]~117
C1L501 = SRAMADDR[1] & SRAMADDR[2] # !SRAMADDR[1] & SRAMADDR[2] & C1_mem[4][7] # !SRAMADDR[2] & C1_mem[0][7];


--C1_mem[6][7] is ram_dp_ar_aw:m1|mem[6][7]
C1_mem[6][7] = DFFEAS(C1L031, CLK,  ,  , C1L602,  ,  ,  ,  );


--C1L601 is ram_dp_ar_aw:m1|data_1_out[7]~118
C1L601 = SRAMADDR[1] & C1L501 & C1_mem[6][7] # !C1L501 & C1_mem[2][7] # !SRAMADDR[1] & C1L501;


--C1L86 is ram_dp_ar_aw:m1|data_1_out[0]~108
C1L86 = SRAMADDR[1] # !SRAMADDR[0];


--C1_mem[1][7] is ram_dp_ar_aw:m1|mem[1][7]
C1_mem[1][7] = DFFEAS(C1L031, CLK,  ,  , C1L241,  ,  ,  ,  );


--C1L701 is ram_dp_ar_aw:m1|data_1_out[7]~119
C1L701 = C1L37 & C1L86 # !C1L37 & C1L86 & C1L601 # !C1L86 & C1_mem[1][7];


--C1_mem[3][7] is ram_dp_ar_aw:m1|mem[3][7]
C1_mem[3][7] = DFFEAS(C1L031, CLK,  ,  , C1L661,  ,  ,  ,  );


--C1L801 is ram_dp_ar_aw:m1|data_1_out[7]~120
C1L801 = C1L37 & C1L701 & C1_mem[3][7] # !C1L701 & C1_mem[5][7] # !C1L37 & C1L701;


--C1L901 is ram_dp_ar_aw:m1|data_1_out~109
C1L901 = SRAMWE & C1L801 & !SRAMCS & !SRAMOE;


--C1L5 is ram_dp_ar_aw:m1|always1~178
C1L5 = RST & !B1_EPP_Wait;


--C1L4 is ram_dp_ar_aw:m1|always1~27
C1L4 = DS & AS & WRITE & C1L5;


--C1_mem[4][6] is ram_dp_ar_aw:m1|mem[4][6]
C1_mem[4][6] = DFFEAS(C1L131, CLK,  ,  , C1L871,  ,  ,  ,  );


--C1_mem[2][6] is ram_dp_ar_aw:m1|mem[2][6]
C1_mem[2][6] = DFFEAS(C1L131, CLK,  ,  , C1L751,  ,  ,  ,  );


--C1_mem[0][6] is ram_dp_ar_aw:m1|mem[0][6]
C1_mem[0][6] = DFFEAS(C1L131, CLK,  ,  , C1L721,  ,  ,  ,  );


--C1L001 is ram_dp_ar_aw:m1|data_1_out[6]~121
C1L001 = SRAMADDR[2] & SRAMADDR[1] # !SRAMADDR[2] & SRAMADDR[1] & C1_mem[2][6] # !SRAMADDR[1] & C1_mem[0][6];


--C1_mem[6][6] is ram_dp_ar_aw:m1|mem[6][6]
C1_mem[6][6] = DFFEAS(C1L131, CLK,  ,  , C1L602,  ,  ,  ,  );


--C1L101 is ram_dp_ar_aw:m1|data_1_out[6]~122
C1L101 = SRAMADDR[2] & C1L001 & C1_mem[6][6] # !C1L001 & C1_mem[4][6] # !SRAMADDR[2] & C1L001;


--C1_mem[5][6] is ram_dp_ar_aw:m1|mem[5][6]
C1_mem[5][6] = DFFEAS(C1L131, CLK,  ,  , C1L981,  ,  ,  ,  );