epptop.fit.summary

在altera fpga中实现epp模式的并口通信程序

Fitter Status : Successful - Tue Dec 30 21:44:00 2008
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : EPPTOP
Top-level Entity Name : EPPTOP
Family : Stratix II GX
Device : EP2SGX30DF780C5
Timing Models : Final
Logic utilization : < 1 %
    Combinational ALUTs : 126 / 27,104 ( < 1 % )
    Dedicated logic registers : 106 / 27,104 ( < 1 % )
Total registers : 106
Total pins : 29 / 406 ( 7 % )
Total virtual pins : 0
Total block memory bits : 0 / 1,369,728 ( 0 % )
DSP block 9-bit elements : 0 / 128 ( 0 % )
Total GXB Receiver Channels : 0 / 8 ( 0 % )
Total GXB Transmitter Channels : 0 / 8 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )