epp2sram.v

在altera fpga中实现epp模式的并口通信程序

//cmd =
//0X1F WRITE BYTE
//0X2F WRITE WORD
//0X4F WRITE 3-BYTE
//0X8F WRITE DWORD
//0X1E READ BYTE
//0X2E READ WORD
//0X4E READ 3-BYTE
//0X8E READ DWORD

//cmd
//   BIT7           BI6       BIT5    BIT4       BIT3     BIT2         BIT1             BIT1
//  1 DWORD
//                1 3BYTE
//                           1 WORD
//                                    1 BYTE
//                                              1 OFFSET
//                                                       1 FUNCTION
//                                                                  1 I2C slave add
//                                                                                   1 WRITE  0 READ

  module EPP2SRAM
   (EPP_Write0,
   EPP_Data,
   EPP_Interrupt,
   EPP_Wait,
   EPP_DataStrobe0,
   EPP_Reset0,
   EPP_AddressStrobe0,

   SRAM_CE,

   SRAM_OE,
 
   SRAM_WE,
  
   SRAM_ADDR,
  
   SRAM_DATA,

   ENV,
   clk);

	//EPP interface signals
	input EPP_Write0;
	inout [7:0] EPP_Data;
	output EPP_Interrupt;
	output EPP_Wait;
	input EPP_DataStrobe0;
	input EPP_Reset0;
	input EPP_AddressStrobe0;
	//
	output SRAM_CE;
	
	output SRAM_OE;

	output SRAM_WE;

	output [2:0]SRAM_ADDR;

	inout  [7:0]SRAM_DATA;

	//
	input clk;
	output ENV;
	

/******************** module regs define ***********************************/
	//regs related to EPP
	reg EPP_Interrupt,EPP_Wait;
	reg EPP_Write,EPP_DataStrobe,EPP_AddressStrobe,EPP_Reset;
	reg [7:0] epp_dataout,epp_datain;
	//
	reg SRAM_CE;
	reg [2:0] sram_raddr,sram_waddr;//sram read write address reg
	
	reg [7:0] sram_dataout;
	

	//internal regs
	
	reg [2:0] epp_state;
	reg [7:0] cmd;//from epp add write     THE REG OF COMMAND
	
	//reg [7:0]raddr_reg[2:0];//slave add;function;offset
	//reg [7:0]waddr_reg[2:0];//slave add;function;offset
	//reg [7:0]rdata_reg[3:0];//byte;word;3-byte;dword
    //reg [7:0]wdata_reg[3:0];//byte;word;3-byte;dword
/**********************  module constant define  *******************************/
	//parameters EPP state
	parameter EPP_IDLE=3'b000,EPP_WAIT_ADDRREAD=3'b001,EPP_WAIT_ADDRWRITE=3'b010,EPP_WAIT_DATAREAD=3'b011,EPP_WAIT_DATAWRITE=3'b100;

    //parameter wrreg_device_add=8'b00000011,wrreg_func_add=8'b00000101,wrreg_offset_add=8'b00001001,rdreg_device_add=8'b00000010,rdreg_func_add=8'b00000100,rdreg_offset_add=8'b00001000;

/*********************  module internal logic  *********************************/

//
always @ (posedge clk)
begin
	if(!EPP_Reset0)
		EPP_Write<=1;
	else
		EPP_Write<=EPP_Write0;
end

always @ (posedge clk)
begin
	if(!EPP_Reset0)
		EPP_DataStrobe<=1;
	else
		EPP_DataStrobe<=EPP_DataStrobe0;
end

always @ (posedge clk)
begin
	if(!EPP_Reset0)
		EPP_AddressStrobe<=1;
	else
		EPP_AddressStrobe<=EPP_AddressStrobe0;
end

always @ (posedge clk)
begin
	if(!EPP_Reset0)
		EPP_Reset<=1;
	else
		EPP_Reset<=EPP_Reset0;
end



//EPP state machine
always @ (posedge clk)
begin
	if(!EPP_Reset0)
	begin
		epp_state<=EPP_IDLE;
		EPP_Interrupt<=0;
		EPP_Wait<=0;
		epp_dataout<=8'b0;
		epp_datain<=8'b0;
		cmd<=8'b0;
		
		sram_raddr<=3'b000;
		sram_waddr<=3'b000;
	
		
		//raddr_reg[2:0]<=8'b0;
		//rdata_reg[3:0]<=8'b0;
		//waddr_reg[2:0]<=8'b0;
		//wdata_reg[3:0]<=8'b0;
	end
	
	else
		case(epp_state)
			EPP_IDLE:
			begin
				epp_state<=EPP_IDLE;
				EPP_Wait<=0;
				if(!EPP_AddressStrobe)
				begin
					if(EPP_Write)
					begin//EPP address read
					    epp_dataout<=cmd[0]?{5'b00000,sram_waddr[2:0]}:{5'b00000,sram_raddr[2:0]};
						/*case(cmd[7:0])//parameter wr_device_add=8'b00000011,wr_func_add=8'b00000101,wr_offset_add=8'b00001001,rd_device_add=8'b00000010,rd_func_add=8'b00000100,rd_offset_add=8'b00001000;
                            wrreg_device_add:  epp_dataout<=waddr_reg[0];
						    wrreg_func_add:    epp_dataout<=waddr_reg[1];
						    wrreg_offset_add:  epp_dataout<=waddr_reg[2];
						    rdreg_device_add:  epp_dataout<=raddr_reg[0];
						    rdreg_func_add:    epp_dataout<=raddr_reg[1];
						    rdreg_offset_add:  epp_dataout<=raddr_reg[2];
						    default:        epp_dataout<=8'b00000000;
						endcase*/
						
						EPP_Wait<=1;
						epp_state<=EPP_WAIT_ADDRREAD;
					end
					else
					begin//EPP address write    cmd come from EPP address write
						cmd<=EPP_Data;  //WRITE COMMAMD FRIST IN REG CMD
						EPP_Wait<=1;
						epp_state<=EPP_WAIT_ADDRWRITE;
					end
				end
				else if(!EPP_DataStrobe)
				begin
					if(EPP_Write)
					begin//EPP data read
						epp_dataout<=SRAM_DATA;//
						EPP_Wait<=1;
						epp_state<=EPP_WAIT_DATAREAD;//
					end
					else
					begin//EPP data write
						epp_datain<=EPP_Data;
						EPP_Wait<=1;
						epp_state<=EPP_WAIT_DATAWRITE;
					end
				end
			end
			
			EPP_WAIT_ADDRREAD:
			begin
				if(EPP_AddressStrobe)
				begin
					EPP_Wait<=0;
					
					epp_state<=EPP_IDLE;
				end
			end
			EPP_WAIT_ADDRWRITE:
			begin
				if(EPP_AddressStrobe)
				begin
					EPP_Wait<=0;
					epp_state<=EPP_IDLE;
				end
			end
			EPP_WAIT_DATAREAD:
			begin
				if(EPP_DataStrobe)
				begin
					EPP_Wait<=0;
					
					epp_state<=EPP_IDLE;
					sram_raddr<=sram_raddr+3'b001;
				end
			end
			EPP_WAIT_DATAWRITE:
			begin
				if(EPP_DataStrobe)
				begin
					EPP_Wait<=0;
					
					epp_state<=EPP_IDLE;
					sram_waddr<=sram_waddr+3'b001;
				end
			end
			default: epp_state<=EPP_IDLE;
		endcase
	end

assign EPP_Data=((epp_state==EPP_WAIT_DATAREAD)||(epp_state==EPP_WAIT_ADDRREAD))?epp_dataout:8'bz;



//cmd resolve


//SRAM 
always @ (posedge clk)
begin
	if(!EPP_Reset0)
	begin
		
		SRAM_CE<=1;
	end
	else
	begin
		
		SRAM_CE<=0;//select SRAM all the time
	end
end



assign SRAM_OE=cmd[0];//cmd's LSM 1->write  0->read
assign SRAM_WE=~cmd[0];

assign SRAM_ADDR=(cmd[0])?sram_waddr:sram_raddr;
assign SRAM_DATA=(cmd[0])?epp_datain:8'bz;


assign ENV=!EPP_Wait&&EPP_Write0&&EPP_DataStrobe0&&EPP_AddressStrobe0&&EPP_Reset0;

endmodule