epptop.map.summary

在altera fpga中实现epp模式的并口通信程序

Analysis & Synthesis Status : Successful - Tue Dec 30 21:43:07 2008
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : EPPTOP
Top-level Entity Name : EPPTOP
Family : Stratix II GX
Logic utilization : N/A
    Combinational ALUTs : 126
    Dedicated logic registers : 106
Total registers : 106
Total pins : 29
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total GXB Receiver Channels : 0
Total GXB Transmitter Channels : 0
Total PLLs : 0
Total DLLs : 0