epptop.fit.qmsg

在altera fpga中实现epp模式的并口通信程序

{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_RCF_CONSTRAINED_ROUTING_ON" "EPPTOP.rcf " "Info: Using constrained routing from file EPPTOP.rcf" {  } { { "EPPTOP.rcf" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.rcf" 1 1 0 } }  } 0 0 "Using constrained routing from file %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.117 ns register register " "Info: Estimated most critical path is register to register delay of 4.117 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns EPP2SRAM:M0\|cmd\[0\] 1 REG LCFF_X49_Y31_N11 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X49_Y31_N11; Fanout = 14; REG Node = 'EPP2SRAM:M0\|cmd\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { EPP2SRAM:M0|cmd[0] } "NODE_NAME" } } { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.516 ns) + CELL(0.507 ns) 1.023 ns EPP2SRAM:M0\|SRAM_ADDR\[0\]~160 2 COMB LCCOMB_X48_Y33_N0 9 " "Info: 2: + IC(0.516 ns) + CELL(0.507 ns) = 1.023 ns; Loc. = LCCOMB_X48_Y33_N0; Fanout = 9; COMB Node = 'EPP2SRAM:M0\|SRAM_ADDR\[0\]~160'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.023 ns" { EPP2SRAM:M0|cmd[0] EPP2SRAM:M0|SRAM_ADDR[0]~160 } "NODE_NAME" } } { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.963 ns) + CELL(0.364 ns) 2.350 ns ram_dp_ar_aw:m1\|mem\[0\]\[6\]~3365 3 COMB LCCOMB_X47_Y31_N8 8 " "Info: 3: + IC(0.963 ns) + CELL(0.364 ns) = 2.350 ns; Loc. = LCCOMB_X47_Y31_N8; Fanout = 8; COMB Node = 'ram_dp_ar_aw:m1\|mem\[0\]\[6\]~3365'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.327 ns" { EPP2SRAM:M0|SRAM_ADDR[0]~160 ram_dp_ar_aw:m1|mem[0][6]~3365 } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.767 ns) + CELL(1.000 ns) 4.117 ns ram_dp_ar_aw:m1\|mem\[0\]\[3\] 4 REG LCFF_X47_Y33_N15 2 " "Info: 4: + IC(0.767 ns) + CELL(1.000 ns) = 4.117 ns; Loc. = LCFF_X47_Y33_N15; Fanout = 2; REG Node = 'ram_dp_ar_aw:m1\|mem\[0\]\[3\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.767 ns" { ram_dp_ar_aw:m1|mem[0][6]~3365 ram_dp_ar_aw:m1|mem[0][3] } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.871 ns ( 45.45 % ) " "Info: Total cell delay = 1.871 ns ( 45.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.246 ns ( 54.55 % ) " "Info: Total interconnect delay = 2.246 ns ( 54.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.117 ns" { EPP2SRAM:M0|cmd[0] EPP2SRAM:M0|SRAM_ADDR[0]~160 ram_dp_ar_aw:m1|mem[0][6]~3365 ram_dp_ar_aw:m1|mem[0][3] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_RCF_SPECIFIED_ROUTE_PORT_ON_ALUT_CANNOT_BE_USED_IN_THIS_MODE" "1597 ram_dp_ar_aw:m1\|data_0_out~1247 DATAE " "Info: Error on line 1597 of Routing Constraints File. Can't use route port DATAE with atom \"ram_dp_ar_aw:m1\|data_0_out~1247\" due to atom's current configuration" {  } { { "EPPTOP.rcf" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.rcf" 1597 1 0 } }  } 0 0 "Error on line %1!d! of Routing Constraints File. Can't use route port %3!s! with atom \"%2!s!\" due to atom's current configuration" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_STATUS_FAILED_DISCONNECTED_RR_GRAPH" "EPP2SRAM:M0\|SRAM_ADDR\[1\]~161 ram_dp_ar_aw:m1\|data_0_out~1247 " "Info: Can't route signal \"EPP2SRAM:M0\|SRAM_ADDR\[1\]~161\" to atom \"ram_dp_ar_aw:m1\|data_0_out~1247\"" { { "Info" "IFITAPI_FITAPI_VPR_CONSTRAINED_ROUTING_USED_FOR_THIS_CONNECTION" "" "Info: Routing for this connection is constrained" {  } {  } 0 0 "Routing for this connection is constrained" 0 0} { "Info" "IFITAPI_FITAPI_VPR_CONSTRAINED_ROUTING_CONSTRAINT_STEP" "1596 " "Info: Error on line number 1596 in Routing Constraints File" {  } { { "EPPTOP.rcf" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.rcf" 1596 1 0 } }  } 0 0 "Error on line number %1!d! in Routing Constraints File" 0 0} { "Info" "IFITAPI_FITAPI_VPR_RCF_REMOVE_WRONG_ROUTING_CONSTRAINT_AND_KEEP_ROUTING" "" "Info: To finish routing, the Quartus II software will remove the routing constraints for this fan-out and will make another attempt at routing this fan-out after all other fan-outs of this signal are routed" {  } {  } 0 0 "To finish routing, the Quartus II software will remove the routing constraints for this fan-out and will make another attempt at routing this fan-out after all other fan-outs of this signal are routed" 0 0}  } {  } 0 0 "Can't route signal \"%1!s!\" to atom \"%2!s!\"" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_RCF_SPECIFIED_ROUTE_PORT_ON_ALUT_CANNOT_BE_USED_IN_THIS_MODE" "1602 ram_dp_ar_aw:m1\|data_0_out~1250 DATAE " "Info: Error on line 1602 of Routing Constraints File. Can't use route port DATAE with atom \"ram_dp_ar_aw:m1\|data_0_out~1250\" due to atom's current configuration" {  } { { "EPPTOP.rcf" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.rcf" 1602 1 0 } }  } 0 0 "Error on line %1!d! of Routing Constraints File. Can't use route port %3!s! with atom \"%2!s!\" due to atom's current configuration" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_STATUS_FAILED_DISCONNECTED_RR_GRAPH" "EPP2SRAM:M0\|SRAM_ADDR\[1\]~161 ram_dp_ar_aw:m1\|data_0_out~1250 " "Info: Can't route signal \"EPP2SRAM:M0\|SRAM_ADDR\[1\]~161\" to atom \"ram_dp_ar_aw:m1\|data_0_out~1250\"" { { "Info" "IFITAPI_FITAPI_VPR_CONSTRAINED_ROUTING_USED_FOR_THIS_CONNECTION" "" "Info: Routing for this connection is constrained" {  } {  } 0 0 "Routing for this connection is constrained" 0 0} { "Info" "IFITAPI_FITAPI_VPR_CONSTRAINED_ROUTING_CONSTRAINT_STEP" "1600 " "Info: Error on line number 1600 in Routing Constraints File" {  } { { "EPPTOP.rcf" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.rcf" 1600 1 0 } }  } 0 0 "Error on line number %1!d! in Routing Constraints File" 0 0} { "Info" "IFITAPI_FITAPI_VPR_RCF_REMOVE_WRONG_ROUTING_CONSTRAINT_AND_KEEP_ROUTING" "" "Info: To finish routing, the Quartus II software will remove the routing constraints for this fan-out and will make another attempt at routing this fan-out after all other fan-outs of this signal are routed" {  } {  } 0 0 "To finish routing, the Quartus II software will remove the routing constraints for this fan-out and will make another attempt at routing this fan-out after all other fan-outs of this signal are routed" 0 0}  } {  } 0 0 "Can't route signal \"%1!s!\" to atom \"%2!s!\"" 0 0}