epptop.map.qmsg

在altera fpga中实现epp模式的并口通信程序

{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always1~4 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always1~4\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always1~5 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always1~5\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always1~6 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always1~6\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always1~7 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always1~7\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always1~8 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always1~8\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always1~9 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always1~9\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always1~10 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always1~10\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always2~2 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always2~2\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always2~3 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always2~3\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always2~4 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always2~4\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always2~5 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always2~5\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always2~6 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always2~6\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always2~7 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always2~7\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always2~8 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always2~8\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ram_dp_ar_aw:m1\|always2~9 ram_dp_ar_aw:m1\|always1~2 " "Info: Duplicate register \"ram_dp_ar_aw:m1\|always2~9\" merged to single register \"ram_dp_ar_aw:m1\|always1~2\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|EPPTOP\|EPP2SRAM:M0\|epp_state 5 " "Info: State machine \"\|EPPTOP\|EPP2SRAM:M0\|epp_state\" contains 5 states" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 82 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|EPPTOP\|EPP2SRAM:M0\|epp_state " "Info: Selected Auto state machine encoding method for state machine \"\|EPPTOP\|EPP2SRAM:M0\|epp_state\"" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 82 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|EPPTOP\|EPP2SRAM:M0\|epp_state " "Info: Encoding result for state machine \"\|EPPTOP\|EPP2SRAM:M0\|epp_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "EPP2SRAM:M0\|epp_state.EPP_WAIT_ADDRREAD " "Info: Encoded state bit \"EPP2SRAM:M0\|epp_state.EPP_WAIT_ADDRREAD\"" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 82 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "EPP2SRAM:M0\|epp_state.EPP_WAIT_ADDRWRITE " "Info: Encoded state bit \"EPP2SRAM:M0\|epp_state.EPP_WAIT_ADDRWRITE\"" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 82 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "EPP2SRAM:M0\|epp_state.EPP_WAIT_DATAREAD " "Info: Encoded state bit \"EPP2SRAM:M0\|epp_state.EPP_WAIT_DATAREAD\"" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 82 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "EPP2SRAM:M0\|epp_state.EPP_IDLE " "Info: Encoded state bit \"EPP2SRAM:M0\|epp_state.EPP_IDLE\"" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 82 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "EPP2SRAM:M0\|epp_state.EPP_WAIT_DATAWRITE " "Info: Encoded state bit \"EPP2SRAM:M0\|epp_state.EPP_WAIT_DATAWRITE\"" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 82 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|EPPTOP\|EPP2SRAM:M0\|epp_state.EPP_IDLE 00000 " "Info: State \"\|EPPTOP\|EPP2SRAM:M0\|epp_state.EPP_IDLE\" uses code string \"00000\"" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 82 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|EPPTOP\|EPP2SRAM:M0\|epp_state.EPP_WAIT_DATAREAD 00110 " "Info: State \"\|EPPTOP\|EPP2SRAM:M0\|epp_state.EPP_WAIT_DATAREAD\" uses code string \"00110\"" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 82 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|EPPTOP\|EPP2SRAM:M0\|epp_state.EPP_WAIT_ADDRWRITE 01010 " "Info: State \"\|EPPTOP\|EPP2SRAM:M0\|epp_state.EPP_WAIT_ADDRWRITE\" uses code string \"01010\"" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 82 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|EPPTOP\|EPP2SRAM:M0\|epp_state.EPP_WAIT_ADDRREAD 10010 " "Info: State \"\|EPPTOP\|EPP2SRAM:M0\|epp_state.EPP_WAIT_ADDRREAD\" uses code string \"10010\"" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 82 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|EPPTOP\|EPP2SRAM:M0\|epp_state.EPP_WAIT_DATAWRITE 00011 " "Info: State \"\|EPPTOP\|EPP2SRAM:M0\|epp_state.EPP_WAIT_DATAWRITE\" uses code string \"00011\"" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 82 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 82 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "ram_dp_ar_aw:m1\|data_0~26 " "Warning: Converting TRI node \"ram_dp_ar_aw:m1\|data_0~26\" that feeds logic to an OR gate" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 31 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "ram_dp_ar_aw:m1\|data_0~30 " "Warning: Converting TRI node \"ram_dp_ar_aw:m1\|data_0~30\" that feeds logic to an OR gate" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 31 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "ram_dp_ar_aw:m1\|data_0~34 " "Warning: Converting TRI node \"ram_dp_ar_aw:m1\|data_0~34\" that feeds logic to an OR gate" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 31 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "ram_dp_ar_aw:m1\|data_0~38 " "Warning: Converting TRI node \"ram_dp_ar_aw:m1\|data_0~38\" that feeds logic to an OR gate" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 31 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "ram_dp_ar_aw:m1\|data_0~42 " "Warning: Converting TRI node \"ram_dp_ar_aw:m1\|data_0~42\" that feeds logic to an OR gate" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 31 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "ram_dp_ar_aw:m1\|data_0~46 " "Warning: Converting TRI node \"ram_dp_ar_aw:m1\|data_0~46\" that feeds logic to an OR gate" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 31 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "ram_dp_ar_aw:m1\|data_0~50 " "Warning: Converting TRI node \"ram_dp_ar_aw:m1\|data_0~50\" that feeds logic to an OR gate" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 31 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "ram_dp_ar_aw:m1\|data_0~54 " "Warning: Converting TRI node \"ram_dp_ar_aw:m1\|data_0~54\" that feeds logic to an OR gate" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 31 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "INT GND " "Warning: Pin \"INT\" stuck at GND" {  } { { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 27 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "M0/epp_state~119 " "Info: Register \"M0/epp_state~119\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "M0/epp_state~120 " "Info: Register \"M0/epp_state~120\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "212 " "Info: Implemented 212 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "183 " "Info: Implemented 183 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "132 " "Info: Allocated 132 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 30 21:43:07 2008 " "Info: Processing ended: Tue Dec 30 21:43:07 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.map.smsg " "Info: Generated suppressed messages file D:/montage/verilog code/EPPTOP V1.0/EPPTOP.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}