epptop.map.qmsg

在altera fpga中实现epp模式的并口通信程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 30 21:43:03 2008 " "Info: Processing started: Tue Dec 30 21:43:03 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off EPPTOP -c EPPTOP " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off EPPTOP -c EPPTOP" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "EPP2SRAM.v(243) " "Warning (10273): Verilog HDL warning at EPP2SRAM.v(243): extended using \"x\" or \"z\"" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 243 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "EPP2SRAM.v(271) " "Warning (10273): Verilog HDL warning at EPP2SRAM.v(271): extended using \"x\" or \"z\"" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 271 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EPP2SRAM.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file EPP2SRAM.v" { { "Info" "ISGN_ENTITY_NAME" "1 EPP2SRAM " "Info: Found entity 1: EPP2SRAM" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 22 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "ram_dp_ar_aw.v(101) " "Warning (10273): Verilog HDL warning at ram_dp_ar_aw.v(101): extended using \"x\" or \"z\"" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 101 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "ram_dp_ar_aw.v(118) " "Warning (10273): Verilog HDL warning at ram_dp_ar_aw.v(118): extended using \"x\" or \"z\"" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 118 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "ram_dp_ar_aw.v(141) " "Warning (10273): Verilog HDL warning at ram_dp_ar_aw.v(141): extended using \"x\" or \"z\"" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 141 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "ram_dp_ar_aw.v(158) " "Warning (10273): Verilog HDL warning at ram_dp_ar_aw.v(158): extended using \"x\" or \"z\"" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 158 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "ram_dp_ar_aw.v(177) " "Warning (10273): Verilog HDL warning at ram_dp_ar_aw.v(177): extended using \"x\" or \"z\"" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 177 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "ram_dp_ar_aw.v(182) " "Warning (10273): Verilog HDL warning at ram_dp_ar_aw.v(182): extended using \"x\" or \"z\"" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 182 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_dp_ar_aw.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram_dp_ar_aw.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_dp_ar_aw " "Info: Found entity 1: ram_dp_ar_aw" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EPPTOP.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file EPPTOP.v" { { "Info" "ISGN_ENTITY_NAME" "1 EPPTOP " "Info: Found entity 1: EPPTOP" {  } { { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "EPPTOP " "Info: Elaborating entity \"EPPTOP\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "EPP2SRAM EPP2SRAM:M0 " "Info: Elaborating entity \"EPP2SRAM\" for hierarchy \"EPP2SRAM:M0\"" {  } { { "EPPTOP.v" "M0" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 58 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "EPP_Reset EPP2SRAM.v(71) " "Warning (10036): Verilog HDL or VHDL warning at EPP2SRAM.v(71): object \"EPP_Reset\" assigned a value but never read" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 71 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram_dp_ar_aw ram_dp_ar_aw:m1 " "Info: Elaborating entity \"ram_dp_ar_aw\" for hierarchy \"ram_dp_ar_aw:m1\"" {  } { { "EPPTOP.v" "m1" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 64 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "EPP2SRAM:M0\|EPP_Interrupt data_in GND " "Warning: Reduced register \"EPP2SRAM:M0\|EPP_Interrupt\" with stuck data_in port to stuck value GND" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 47 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}