epptop.hif

在altera fpga中实现epp模式的并口通信程序

Version 7.0 Build 33 02/05/2007 SJ Full Version
33
1775
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
EPP2SRAM
# storage
db|EPPTOP.(1).cnf
db|EPPTOP.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
EPP2SRAM.v
8b517bba98a096303f52b0e4b6296536
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
EPP_IDLE
000
PARAMETER_UNSIGNED_BIN
DEF
EPP_WAIT_ADDRREAD
001
PARAMETER_UNSIGNED_BIN
DEF
EPP_WAIT_ADDRWRITE
010
PARAMETER_UNSIGNED_BIN
DEF
EPP_WAIT_DATAREAD
011
PARAMETER_UNSIGNED_BIN
DEF
EPP_WAIT_DATAWRITE
100
PARAMETER_UNSIGNED_BIN
DEF
}
# hierarchies {
EPP2SRAM:M0
}
# end
# entity
ram_dp_ar_aw
# storage
db|EPPTOP.(2).cnf
db|EPPTOP.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ram_dp_ar_aw.v
7844fbffcb42c7ea127fe81cdd123846
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
ram_dp_ar_aw:m1
}
# end
# entity
EPPTOP
# storage
db|EPPTOP.(0).cnf
db|EPPTOP.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
EPPTOP.v
a2716d68f189228a2df399e6ae37ab8
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
|
}
# end
# complete